Receiving circuit reset upon reception of burst data and transmi

Details Receiving circuit reset upon reception of burst data and transmi Receiving circuit reset upon reception of burst data and transmi

1994-09-29

1997-04-01

Heckler, Thomas M.

395881, G06F 1342

Patent

active

056175620

ABSTRACT:
A transmission and reception system includes a transmitting unit and a receiving unit. The transmitting unit transmits a transmission signal including at least a data signal and a clock signal. The data signal is transmitted at a random timing. The receiving unit includes a delay unit for delaying the data signal by a predetermined time period in synchronous with the clock signal. A buffer unit operates in synchronous with the clock signal, temporally stores the data of the delayed data signal and outputs the data. A control units operates in synchronous with the clock signal, controls the storing and outputting operations of the buffer unit. A reset unit operates in synchronous with the clock signal, supplies a reset signal at start timing of the data signal to reset the control unit.

REFERENCES:
patent: 4426685 (1984-01-01), Lorentzen
patent: 4884286 (1989-11-01), Szcdzepanek et al.
patent: 5287025 (1994-02-01), Nishimichi

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