Multiplex communications – Wide area network – Packet switching
Patent
1993-09-24
1995-02-07
Safourek, Benedict V.
Multiplex communications
Wide area network
Packet switching
375100, 375108, 455133, H04B 708
Patent
active
053881001
ABSTRACT:
A receiving circuit, which prevents spikes included in reproduced clock signals, caused by a time slot change in the division multiplex wireless communication or by the switching of diversity antenna, from being transmitted to the following circuits, and thereby eliminates errors in the determination of the received data, has a demodulator coupled to an antenna for demodulating signals received therefrom, a selector coupled to the demodulator for selecting from a plurality of clock signals reproduced from the data of the respective time slots, one of the reproduced clock signals. A time division timing control circuit is coupled to the selector and to a switching circuit, which control circuit is supplied with an internal clock signal from an internal clock generation circuit. The switching circuit is coupled to the output terminal of the selector and selects and outputs either the internal clock signal or the selected reproduced clock signal. The receiving circuit may be provided with a diversity control circuit.
REFERENCES:
patent: 4369515 (1983-01-01), Valdes
patent: 4574377 (1986-03-01), Miyazaki et al.
patent: 4651103 (1987-03-01), Grimes
patent: 4953163 (1990-08-01), Miyamoto et al.
patent: 5239541 (1993-08-01), Murai
Fujitsu Limited
Safourek Benedict V.
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