Pulse or digital communications – Receivers
Reexamination Certificate
1998-11-13
2002-12-10
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
C375S224000, C375S317000, C455S130000, C714S043000
Reexamination Certificate
active
06493401
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to a Controlled Area Network and more particularly to a receiving circuit and method for such a network.
BACKGROUND OF THE INVENTION
A Controlled Area Network (CAN) system is provided for motor vehicles and comprises a plurality of transmitters and receivers interconnected via a bus line system. This allows control systems, sensors, measurement transducers and receivers, control signal receivers, actuating means etc. to be linked to each other.
For reasons of safety, a preferred CAN system performs a digital data transfer via a double-line bus having two lines, with the pulse signals to be transmitted being transmitted simultaneously via both lines and being synchronous in terms of pulse times and pulse length thereof, but opposite in terms of logic value. This provides a transfer redundance ensuring an error-free data transfer also in case of numerous error conditions of the bus system. Such errors are line interruptions, line short circuits towards battery voltage or ground and mutual short circuits between the two lines of the double-line bus.
A known receiving circuit comprising such a double-line bus system is known, for example, in the form of integrated circuit PCA82C252 of Philips.
FIG. 6
shows in a block diagram the essential components of this known receiving circuit of interest here. The known circuit comprises two terminals for connection to a first line CANH and for connection to a second line CANL of the double-line bus, respectively. CANH is connected to a non-inverting input of a comparator COMP
1
via an offset voltage source Voffset, and CANL is connected directly to an inverting input of comparator COMP
1
. Voffset superimposes an offset voltage of +2.8V on the pulse signal received via CANH. The pulse signal received via CANH furthermore is fed to non-inverting inputs of comparators COMPS
2
and COM
4
. The pulse signal received via CANL is fed to a non-inverting input of a comparator COMP
3
and to an inverting input of a comparator COMP
5
. The inverting inputs of COMP
2
and COMP
3
are connected to a reference voltage source REF
1
supplying to these inverting inputs a reference voltage of +5V. By means of a reference voltage source REF
2
, a reference voltage of +2.8V is fed to the inverting input of COMP
4
and to the non-inverting input of COMP
5
.
The outputs of comparators COMP
1
, COMP
4
and COMP
5
are connected to three different inputs of a switching means SW connected on its output side to an output terminal RxD of the receiving circuit. Switching over of switching means SW is controlled by a multiplex control logic circuit MUX comprising a first input E
1
connected to the output of COMP
2
, a second input E
2
connected to the output of COMP
3
and a third input E
3
. E
3
is connected to the input of a timer T having its input connected to the output side of switching means SW.
The mode of operation of this known receiving circuit will now be elucidated with the aid of
FIGS. 7
to
9
. Eight possible modes of operation will be considered depending on the condition of the double-line bus, namely:
case 1: lines CANH and CANL operate properly
case 2: line CANH is interrupted
case 3: line CANL is interrupted
case 4: line CANH is short circuited to battery
case 5: line CANL is short circuited to ground
case 6: line CANH is short circuited to ground
case 7: line CANL is short circuited to battery
case 8: lines CANL and CANH are short circuited to each other.
The mode of operation of the receiving circuit will now be discussed briefly for these cases.
FIGS. 7
to
9
each show the pulse signal on CANL, the pulse signal on CANH, and in broken lines the pulse signal of CANH increased by +Voffset, and the output signal of the receiving circuit arising at RxD. For the sake of brevity and simplicity, the individual signals are designated only with the names of the associated lines and terminals, respectively.
The mode of operation of the known receiving circuit according to
FIG. 6
will now be elucidated briefly with respect to the eight cases indicated.
Case 1
The associated signal paths are shown in FIG.
7
. As soon as the potential of CANL reaches the value of CANH+Voffset, the output signal of the receiving circuit changes from a high to a low logic value. When CANL thereafter drops again below CANH+Voffset, the output of the receiving circuit changes from a low to a high logic value. The data content contained in CANH thus is reflected on the output of the receiving circuit.
Case 2
When line CANH is interrupted, a low logic value appears at the corresponding input terminal of the receiving circuit. The reason therefor is that the inputs of the receiving circuit connected to CANH and CANL are preceded by shunt resistors connecting CANH to ground and CANL to the positive voltage +5V, which constitutes the potential value of the high logic value. When line CANH is interrupted, the corresponding input terminal of the receiving circuit thus is connected to ground via the associated shunt resistor.
The related signal diagram in
FIG. 8
shows that in this case the potential of CANH remains constant on a low value and CANH+Voffset thus remain on a correspondingly increased constant value. As the pulse signal of CANL still exceeds and then falls below the threshold value established by CANH+Voffset, a usable and correct pulse signal is still created at the output terminal RxD.
Case 3
When line CANL is interrupted, the corresponding input terminal of the receiving circuit is raised to +5V via the associated shunt resistor, and this voltage value is fed to the inverting input of comparator COMP
1
in constant manner. This is shown in the signal diagram in FIG.
9
. Due to the fact that the constant potential value of CANL in this case crosses the potential path CANH+Voffset, a pulse signal is created at output terminal RxD which contains the information of the pulse signal received via CANH and is only inverted with respect to the pulse signal on the output side which is obtained for cases 1 and 2.
Case 4
A short circuit of CANH towards a voltage of more than 5V is determined with the aid of comparator COMP
2
. The signal occurring at the output thereof during such determination effects via multiplex logic control circuit MUX switching over of the switching means SW to the output of comparator COMP
5
. The receiving circuit now operates in a single-line mode using the pulse signal arriving via CANL and deciding whether this pulse signal is greater or smaller than the reference voltage of 2.8V.
Case 5
When CANL is short circuited to ground, this results in a permanent dominant voltage level at output RxD, i.e., a voltage level that is permanently lower than the switching threshold value CANH+Voffset and thus the sum of the pulse signal voltage entering via CANH and the offset voltage. As the CAN protocol prescribes a logic value change of the pulse signals transferred at the latest after a predetermined period of time after beginning of the particular pulse., the condition that a logic value change no longer occurs at output RxD, constitutes a violation of the CAN protocol. For monitoring such a violation, timer T is provided. When the latter detects no logic value change at output RxD after a predetermined delay time, timer T via multiplex logic control circuit MUX effects switching over of switching means SW such that RxD is connected to the output of COMP
4
, so that as of this moment only a single-line operation takes place, evaluating the pulse signals arriving via CANH. Until the timer has responded and effected switching over to such single-line operation, data transferred, however, have been missed. It is thus necessary to retransfer these data from the transmitting point. This means that a certain amount of the data transmitted always has to be stored on the transmitter side in order to permit retransmitting to the receiving circuit in case of this error.
Case 6
A short circuit of CANH to ground leads to the same conditions and the sam
Chin Stephen
Johnson Brian L
Jorgenson Lisa K.
Liu Shuwang
Seed IP Law Group PLLC
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