Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-09-19
2002-08-06
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S543000
Reexamination Certificate
active
06429717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiving circuit of a signal transfer system and a semiconductor device in which the signal transfer system is applied, and more particular it relates to a receiving circuit of a signal transfer system performing signal transfer between LSI chips, between modules, and between a plurality of circuits within one and the same LSI chip, and to a semiconductor device in which this signal transfer system is applied.
2. Related Art
In recent years, there has been a demand for signal transfer with a high speed between, for example, a DRAM and a processor, or between circuits within a single semiconductor integrated circuit. The reason for this is that, with a dramatic improvement in the operating speed of CMOS LSI devices in recent years, microprocessors with clock frequencies exceeding 1 GHz being reported, the processing speed of equipment making use of these high-speed LSI devices has come to be restricted by the transfer speed between circuit boards, and between chips.
For example, in a personal computer in order to improve the signal processing speed from a DRAM to a processor, the improvement of the parallel transfer rate per pin to the gigabit level and beyond is being studied. In order to send such as high-speed signal outside the chip, it is necessary to take measures with respect to the significant deterioration of a signal waveform from the ideal transmitted signal waveform caused by attenuation and reflection in the transmission path, including the package and connectors.
FIG. 14
of the accompanying drawings shows a receiving end waveform of a signal transmitted on a transmission path. The transmitted signal undergoes multiple reflections along the transmission line and attenuation, the result being that a certain amount of time is required to reach the potential at the transmitting end. Given this situation, let us assume that the transmission path can be approximated by a circuit made up of lumped constants, in which the bit length of the transmitted signal is T, and the time constant of the transmission line is &tgr;. In the example shown in the drawing, the bit length T is shorter than the time constant of the transmission path (T<&tgr;), in response to data changes (time slot “n”), data undergoes a new change (time slot “n+1) at time T during which the signal voltage at the receiving end is changing. If the potential at the time n+1 is V(n+1) and the potential at the time n is V(n), because the potential change can be expressed by the relationship V(n+1)=V(n) (1−exp(−T/&tgr;)), in the case in which the time constant of the transmission path is longer than the bit length of the transmitted signal, it can be seen that there is a large change in the signal at the receiving end because of the influence of the past logic state of the signal. In particular in the case in which the transmitted signal remains at the 0 or 1 state continuously, with a subsequent single-bit reversal to the other logic state, the received signal does not reach a logic signal level enabling sufficient discrimination by a discrimination circuit, thereby resulting in an erroneous judgment by the discriminating circuit.
In order to solve such problems, one method is to simply use a transmission medium having superior high-frequency characteristics. Such a transmission medium, however, generally not only has a high cost, but also requires a large amount of mounting space, thereby resulting in the problem of an increased size of the system. As shown in the Japanese unexamined patent publication (KOKAI) No.10-275038, the Japanese Utility Model (KOKOKU) No.5-46366 and IECE C-II, Vol. J82-C-II, No. 5 pp. 239-246, there is a method of storing the past signal states in shift registers or the like, and applying weighting to these information to change the level of a reference signal. The circuit configuration in disclosed in the above-mentioned IECE C-II, Vol. J82-C-II, No. 5 pp. 239-246 is shown in FIG.
15
. Because the results of a judgment made by the first latch stage of the receiving circuit are successively stored into a shift register, the each output bit of the shift register represents the past received signal. In the example shown in the drawing, a 2-bit shift register
26
is used to store past signal information, this information being used for changing the level of a reference signal, using a D/A converter
23
to act as a weighting circuit. The first latch stage of the shift register has a differential circuit configuration that performs a comparison with a reference signal and a received signal, to be described later, and the output of this latch circuit is the output of the receiving circuit. The weighting circuit in this example is a circuit which outputs an average value of a plurality of signals.
To simplify the description of the operation of the circuit of
FIG. 15
, consider the case in which signal information for the immediately previous two bits is not weighted. In this case, if the two bit previous signals and one bit previous signal are both at the 0 level, the weighting circuit outputs a low level as the reference potential. If the either one of two bit previous signals and one bit previous signal is at the 1 level and the other is at the 0 level, the reference potential would be an intermediate potential, and if the two bits previous signals and one bit previous signal are both at the 1 level, the reference potential would be at the high level.
FIG. 16
of the accompanying drawings shows the signal waveform at the receiving end, the logic discrimination reference voltage of this circuit, the logic value at the transmitting end, and the logic value judged by this circuit, for the case in which the data period T is 0.5&tgr;. It can be seen that, although the signal waveform is considerably deteriorated at the receiving end, because the reference signal used for logic discrimination is set to the average value of a past data series, a potential appropriate for logic discrimination is achieved, making it possible to receive the signal without erroneous logic level discrimination. In this drawing, the potential in which the reference voltage is constant is shown. The white characters on black background in
FIG. 16
indicates erroneous discrimination.
In the example of this circuit, the change in level of the reference signal is 1/4 of the signal amplitude, and in the case of a transmission medium having poor frequency characteristics, it is necessary to adjust for an even narrower signal level. To make a finer signal adjustment, it is necessary to increase the number of level shift register stages and input each output bit thereof to a weighting circuit. For example, in the case of using a 3-bit shift register, it is possible to establish 5 levels of reference potential.
Using this method, there is the drawback that, if the number of shift register stages is made large and the reference signal level is controlled even more finely, if even one erroneous discrimination occurs, this erroneous discrimination will continue for a long period.
In order to avoid this problem, a configuration as shown in
FIG. 17
of the accompanying drawings has been proposed. This circuit uses two RZ signals, performs analog storage of the 1-bit previous signal level into a capacitor, and subtracts the 1-bit previous signal level from the current signal level, so as to eliminate the influence of the past signal, and it performs logic level discrimination. The operation of this circuit is described below, with reference made to FIG.
17
.
In the case in which the clock signal &phgr;1 is at a high level, the input voltage Vn−1 in the receiving circuit at the time “n−1” and the reference potential VTT are received by the capacitors C
1
and C
2
, simultaneously with which the input and output of an inverter are shorted (
FIG. 17
(
a
)). The output potential of the inverter with the input and output thereof shorted is the logic threshold of that inverter. Next, in t
Callahan Timothy P.
Nguyen Linh
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