Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
2000-03-06
2001-09-04
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C370S509000
Reexamination Certificate
active
06285724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiving apparatus and a communication system for receiving a serial signal and decoding the received serial signal into an information signal including information data. More specifically, the present invention relates to a receiving apparatus and a communication system capable of decoding a received serial signal into an information signal including information data even if noise is included in the received serial signal.
2. Description of the Related Art
In a serial data transmission method in which a plurality of information bits are transmitted serially, the following so-called start stop synchronization method is used. In this method, transmission is made asynchronously so that a start bit and a stop bit are added respectively before and after data for identification of the beginning and the end of a frame, and then, the start bit is detected at a receiving station for frame synchronization.
According to the above-mentioned prior art serial data transmission method, if a noise signal (pulse) is included before the start bit, it is such a possibility that the noise signal (pulse) may be detected as the start bit. Further, if the noise signal (pulse) is included within the data, it is such a possibility that the noise signal (pulse) may be detected as valid data.
Attempts have been made in order to avoid the above-mentioned problems, and the following method. for receiving serial data is disclosed in Japanese Patent Laid-Open Publication No. 6-152576. If noise is expected in a received signal, a signal having a pulse width not greater than a predetermined pulse width are eliminated as a noise signal from the received signal so that the noise will not cause any detection error, thus a noise signal is eliminated from the received signal, and frame-synchronized data is obtained based on the noise-eliminated signal.
In addition, a method for correcting a bit drop or the like from a run-in signal is disclosed in Japanese Patent Laid-Open Publication No. 58-42336.
The above-mentioned prior art receiving apparatus has the following problems. With the arrangements described above, the prior art receiving apparatus cannot remove a noise signal (pulse) if the noise signal (pulse) has a width similar to that of the valid signal. Therefore, if a noise signal (pulse) having a pulse width similar to that of the synchronizing signal exists near the synchronizing signal, the noise signal (pulse) may be detected as a start pulse. Further, if a noise signal (pulse) having a pulse width similar to that of the data signal exists in the data, the noise pulse may be detected as a valid data signal.
In order to prevent such an error detection, there is such an idea of increasing the pulse width of the synchronizing signal or the data signal. In this case, the increased pulse width of the synchronizing signal or of the data signal decreases transmission speed or the amount of data transmittable within a given time interval.
SUMMARY OF THE INVENTION
An essential object of the present invention is therefore to provide a communication system and a receiving apparatus for the communication system, each of which is capable of performing correct detection of the synchronizing signal or correct decoding the information signal (data signal) even with presence of the noise signal, without significant decrease in the transmission speed.
In order to achieve the aforementioned objective, according to one aspect of the present invention, there is provided a receiving apparatus for receiving a serial signal composed of a sequence of signals transmitted through a transmission medium, comprising:
a receiving circuit for receiving as a received signal a serial signal, which is a sequence of signals including at least one of a synchronizing signal and an information signal, and which includes a plurality of signals being the same as each other and being apart from each other by a predetermined time interval;
a delaying circuit for generates a delayed signal by delaying the received signal received by the receiving circuit by the predetermined time interval;
a multiplying circuit for generating a multiplied signal by multiplying the received signal by the delayed signal; and
a detecting circuit for detecting at least one of the synchronizing signal and the information signal, based on the multiplied signal.
In the above-mentioned receiving apparatus, each of the plurality of signals is preferably the synchronizing signal, and the detecting circuit detects the synchronizing signal based on the multiplied signal.
In the above-mentioned receiving apparatus, the detecting circuit preferably detects the information signal from the received signal, based on the detected synchronizing signal.
In the above-mentioned receiving apparatus, each of the plurality of signals is preferably the information signal, and the detecting circuit detects the information signal based on the multiplied signal.
In the above-mentioned receiving apparatus, the plurality of signals preferably include first, second and third signals being the same as each other and being apart from each other by predetermined time intervals. The delaying circuit generates a first delayed signal by delaying the received signal by a time interval equal to a time interval between the first and third signals, and generates a second delayed signal by delaying the received signal by a time interval equal to a time interval between the second and third signals. The multiplying circuit generates a multiplied signal by multiplying the first and second delayed signals by the received signal.
In the above-mentioned receiving apparatus, each of the first signal, the second signal and the third signal is preferably the synchronizing signal, and the detecting circuit detects the synchronizing signal based on the multiplied signal.
In the above-mentioned receiving apparatus, the detecting circuit preferably detects the information signal from the received signal, based on the detected synchronizing signal.
In the above-mentioned receiving apparatus, the time interval between the first and second signals is preferably different from the time interval between the second and third signals.
In the above-mentioned receiving apparatus, the serial signal preferably includes the following signals:
(a) a plurality of first signals, each of which is the synchronizing signal, which are the same as each other, and which are apart from each other by a predetermined time interval; and
(b) a plurality of second signals, each of which is the information signal, which are the same as each other, and which are apart from each other by the predetermined time interval.
The multiplying circuit generates a first multiplied signal by multiplying the synchronizing signal of the received signal by at least one delayed signal of the synchronizing signal based on the plurality of first signals, and generates a second multiplied signal by multiplying the information signal of the received signal by at least one delayed signal of the information signal based on the plurality of second signals. The detecting circuit detects the synchronizing signal based on the first multiplied signal, and detects the information signal from the second multiplied signal based on the detected synchronizing signal.
In the above-mentioned The receiving apparatus, the delaying circuit preferably comprises:
an A/D converter for converting the analog received signals into digital signals;
a digital memory for sequentially storing digital signals converted by the A/D converter;
a D/A converter for converting the digital signals stored in the digital memory into analog signals; and
a timing generator for generating timing signals for controlling the A/D converter, the digital memory and the D/A converter to delay the analog received signals by the predetermined time interval and output delayed signals.
According to another aspect of the present invention, there is provided a communication system comprising:
a transmitting apparatus for tran
Shimada Takashi
Taniguchi Yasunori
Mitsubishi Denki & Kabushiki Kaisha
Pham Chi
Phu Phuong
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