Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal detecting using a clock signal
Reexamination Certificate
2001-03-23
2003-02-11
Edun, Muhammad (Department: 2653)
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal detecting using a clock signal
C369S047280, C369S047480
Reexamination Certificate
active
06519218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiving apparatus for receiving data and a method of the same, to a recording apparatus for recording input data on a recording medium and a method of the same, and to a data recording system.
2. Description of the Related Art
A plurality of optical disk drives or other recording apparatuses are sometimes connected for transfer of data or a plurality of recording apparatuses are sometimes used for simultaneously recording data. The conventional method in such cases will be explained with reference to FIG.
1
.
FIG. 1
is a schematic view of the configuration of an example of a data recording system of the related art.
This data recording system
90
comprises recording apparatuses
60
to
80
. The recording apparatuses
60
and
70
are connected to each other by a transmission line
6
D, while the recording apparatuses
70
and
80
are connected to each other by a transmission line
7
D.
The recording apparatuses
70
and
80
reproduce a clock signal CLK from the transmission lines
6
D and
7
D by phase locked loop (PLL) circuits
72
and
82
and receive data by using the clock signal CLK.
The recording apparatus
60
comprises a crystal oscillator
61
, amplifiers
62
and
66
, a data processor
63
, a data equalizer
64
, and a write device
65
.
The crystal oscillator
61
and the amplifier
62
comprise a clock signal generation circuit for generating a reference clock signal CK and provide the reference clock signal CK to the data processor
63
.
The data processor
63
generates serial data DT and the clock signal CLK based on the reference clock signal CK.
The data equalizer
64
equalizes the serial data DT based on the clock signal CLK and outputs it to the write device
65
.
The write device
65
writes the serial data supplied from the data equalizer
64
on the recording medium
69
. For example, the write device
65
is an optical disk drive and the recording medium
69
is an optical disk.
The amplifier
66
amplifies the serial data DT from the data processor
63
and outputs it to an output terminal T
66
.
The output terminal T
66
of the recording apparatus
60
and an input terminal T
71
of the recording apparatus
70
are connected to each other by the transmission line
6
D.
The recording apparatus
70
comprises amplifiers
71
and
76
, a PLL circuit
72
, a D-type flip-flop (DFF)
73
, a data equalizer
74
, and a write device
75
.
The amplifier
71
amplifies serial data from the input terminal T
71
to generate serial data DTA and supplies the serial data DTA to the PLL circuit
72
and a data input terminal of the DFF
73
.
The PLL circuit
72
generates a clock signal CLK based on the serial data DTA and supplies the clock signal CLK to a clock input terminal of the DFF
73
and the data equalizer
74
.
The DFF
73
latches the serial data DTA based on the clock signal CLK and supplies the latched data to the data equalizer
74
as serial data DT.
The data equalizer
74
equalizes the serial data DT based on the clock signal CLK and outputs it to the write device
75
.
The write device
75
writes the serial data supplied from the data equalizer
74
on the recording medium
79
. For example, the write device
75
is an optical disk drive and the recording medium
79
is an optical disk.
The amplifier
76
amplifies the serial data DT from the DFF
73
and outputs it to an output terminal T
76
.
The output terminal T
76
of the recording apparatus
70
and an input terminal T
81
of the recording apparatus
80
are connected to each other by the transmission line
7
D.
The recording apparatus
80
comprises amplifiers
81
and
86
, a PLL circuit
82
, a D-type flip-flop (DFF)
83
, a data equalizer
84
, and a write device
85
.
The write device
85
of the recording apparatus
80
writes data on a recording medium
89
. For example, the write device
85
is an optical disk drive and the recording medium
99
is an optical disk.
The amplifiers
81
and
86
, the PLL circuit
82
, the D-type flip-flop (DFF)
83
, the data equalizer
84
, and the write device
85
of the recording apparatus
80
have the same configurations as the amplifiers
71
and
76
, the PLL circuit
72
, the D-type flip-flop (DFF)
73
, the data equalizer
74
, and the write device
75
, so the explanations of these portions having the same configurations are omitted.
Summarizing the problem to be solved by the invention, in the recording apparatus
70
, the output data DT from the DFF
73
is influenced by the jitter of the clock signal CLK generated in the PLL circuit
72
.
In the recording apparatus
80
, the output data DT from the DFF
83
is influenced by the jitter of the clock signal CLK generated in the PLL circuit
72
and the jitter of the clock signal CLK generated in the PLL circuit
82
.
Therefore, when further recording apparatuses are connected to an output terminal T
86
of the recording apparatus
80
, it becomes difficult to accurately record the data DT generated at the data processor
63
on all recording media because of the accumulation of the jitter.
On the other hand, there is a synchronized receiving method in which both of the clock signal and the serial data are supplied to the receiving apparatus to prevent the jitter of the clock signal caused by the PLL circuit.
In this synchronized receiving method of the related art, however, the clock signal and the data must be accurately synchronized under a predetermined phase relationship. In practice, however, the phase of the data actually input from the outside is often off from the clock signal. Further, the amount of the deviation is not apparent. Therefore, such a synchronized method cannot be applied in the many cases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a receiving apparatus and method able to suitably receive data even if the phase of the data and the phase of the clock signal are offset.
Another object of the present invention is to provide a recording apparatus and method able to suitably record input data on a recording medium even if the phase of the input data and the phase of the clock signal are offset.
Still another object of the present invention is to provide a data recording system able to suitably record input data on a recording medium even if the phase of the input data and the phase of the clock signal are offset.
According to a first aspect of the present invention, there is provided a receiving apparatus comprising a receiving circuit for receiving data synchronized with a predetermined clock signal; a data detection circuit for detecting values of at least three bits of received data in a cycle defined by a period started from a desired position and corresponding to a cycle of the clock signal; and a selecting circuit for selecting from the received data with the detected values the received data with the least change of the value with respect to the received data of values detected immediately before and after substantially in each cycle and outputting the value of the received data.
Preferably, the selecting circuit detects the longest period when the same value continues based on the detected values of the plurality of bits of received data and selects the received data of the approximate center of the period.
More preferably, the data detection circuit detects the values of the plurality of bits of received data in synchronization with the clock signal at every predetermined interval less than ½ of the cycle of the clock signal.
Still more preferably, the data detection circuit successively delays the received data to generate M (M is an integer of 4 or more) number of bits of delayed data and latches the M number of bits of delayed data in synchronization with the clock signal substantially simultaneously to detect the values of the M number of bits of the received data, and the selecting circuit selects from the M number of the received data with values detected and successively delayed the received data of the approximate center o
Edun Muhammad
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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