Telecommunications – Receiver or analog modulated signal frequency converter – Signal selection based on frequency
Patent
1988-10-25
1991-04-16
Eisenzopf, Reinhard J.
Telecommunications
Receiver or analog modulated signal frequency converter
Signal selection based on frequency
455310, H04B 110
Patent
active
050089552
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to a receiver which selects a station relying upon station selecting data produced from a microcomputer and more particularly to a receiver which can increase an S/N ratio during the reception by automatically stopping the operation of a clock pulse generator in the microcomputer when the station selecting operation is finished.
2. Background Art
An example of an FM radio receiver in the prior art shown in FIG. 1 will be described.
Referring to the same figure, an FM broadcast signal (in a range of 76 to 90 MHz in Japan) received at an antenna 1 is supplied to a front end 2. An intermediate frequency signal delivered from the front end 2 is supplied through an intermediate frequency amplifier 3 to an FM detector 4. A stereo mixed-wave signal delivered from the FM detector 4 is supplied to a stereo multiplex decoder (stereo demodulator) 5 by which left- and -right audio signals are developed at output terminals 6L and 6R led out from the stereo multiplex decoder 5, respectively.
Reference numeral 7 denotes a PLL (phase-locked loop) circuit. As is well known (not shown in detail), a local oscillation signal Fout from the front end 2 is divided by N in a -1/N frequency-divider provided within the PLL circuit 7 and compared with a reference oscillation signal. The compared error signal therefrom is supplied through a low-pass filter to the front end 2 as a tuning control voltage Vt. Reference numeral 8 designates a controller that might be formed of a microcomputer. The fact that the dividing ratio of the 1/N frequency-divider in the PLL circuit 7 can be controlled by the controller 8 is carried out by using the system disclosed in U.S. Pat. No. 4592078 "UP/DOWN COUNTER CONTROL CIRCUIT" and such a control operation therefore need not be described in detail. The controller 8 is connected with a crystal oscillator 9 forming a clock signal generator which generates a clock signal with frequency of several MHz, for example, 4 MHz. One and the other ends of the crystal oscillator 9 are grounded via capacitors 10 and 11, respectively. A key input apparatus 12 is connected to the controller 8, and a station selection or the like is carried out by operating the key switch of the key input apparatus 12. When a station is selected, the controller 8 supplies data indicative of N for the frequency-dividing ratio 1/N to the PLL circuit 7, thus changing the frequency-dividing ratio 1/N to select the station. In practice, the data indicative of N corresponding to the receiving frequency is supplied from the controller 8 to the PLL circuit 7 in synchronism with the clock signal. After data N of predetermined bits is transferred, a latch signal is supplied thereto so that the data N is latched to a data register connected to the 1/N frequency-divider in the PLL circuit 7, thus the frequency-dividing ratio 1/N being changed to select the station.
A display apparatus 13 is connected to the controller 8, and the display apparatus 13 is supplied with display data when a station is selected and so on. The display displays a channel of a station selected or the like. In practice, display data is supplied from the controller 8 to the display apparatus 13 in synchronism with the clock signal and the latch signal is finally supplied thereto, whereby the display apparatus 13 latches and displays the display data.
The controller 8 supplies a switching signal of, for example, narrow band and wide band to the intermediate frequency amplifier 3 so that the band width thereof is controlled.
In the FM radio receiver of the example shown in FIG. 1, during the reception, the controller 8 successively generates clock signals so that the harmonic componets of the 4 MHz clock signal are supplied to the front end 2. There is a risk that a beat interference with the receiving frequency will be caused. To avoid such a defect, in the art there is such a limitation or the like that a substrate for a signal system and a substrate for a digital system such as the microcomputer or the like have
REFERENCES:
patent: 4276654 (1981-06-01), Nations et al.
patent: 4281349 (1981-07-01), George
patent: 4301540 (1981-11-01), Sato et al.
patent: 4384361 (1983-05-01), Masaki
patent: 4592078 (1986-05-01), Yamada
Eisenzopf Reinhard J.
Sony Corporation
Urban Edward
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