Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-03-06
2001-08-14
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S108000, C327S206000
Reexamination Certificate
active
06275082
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to noise suppression and more particularly, to an apparatus and method for noise suppression by employing hysteresis.
2. Description of the Related Art
Analog circuits often include noisy signals. Noisy signals may result in bit errors when converting the analog signals to digital signals. Noise suppression can reduce noise. For example, in receiver circuits that convert (noisy) analog input signals to digital on-chip signals hysteresis is one desired means to suppress noise. In instances of slope reversal of ill terminated signal traces and extremely slow transitions (e.g., in burn-in test setups for semiconductor device tests) superimposed with random noise can cause incomplete pulses and spikes of the on-chip digital signals. This can cause malfunction of circuitry that assumes certain minimum and maximum pulse widths.
A structure of a differential amplifier-based receiver is shown in
FIG. 1. A
first stage
10
includes an N-channel differential pair
11
with a P-channel current mirror
13
. A second stage
12
is realized by an inverter
14
. One advantage of this configuration is that a switch-point is very well defined by the reference voltage VREF. The switch-point is the input voltage level (VIN) at which the output switches. For good system performance, a hysteresis of about 5-10% of the input voltage (VIN) swing is desirable. For stub series terminated logic (SSTL-2, for example), this would be about a few tens of mV's.
The prior art realization of receivers with hysteresis does not typically provide sufficient hysteresis control. The prior art provides weak controllability (i.e. achieving a small shift of the switch point based on the output state) or slow reaction time (i.e. capability to suppress fast noise spikes).
In U.S. Pat. No. 5,796,281, adding additional current to an output node of a first stage (differential amplifier) creates hysteresis. Note however, that the amount of current added is not well controlled and thus the amount of hysteresis is not well controlled. To achieve small hysteresis the transistors (for example, Q2 in U.S. Pat. No. 5,796,281) that switch the additional current have to be a small fraction of the size of main transistors of the amplifiers in U.S. Pat. No. 5,796,281. For speed purposes, however, these transistors are close to their minimum size already. Thus, it is very difficult, if not impossible, to achieve small and controlled amounts of hysteresis. Note that a hysteresis, which is too large, will also adversely affect speed. FIGS. 26.4 and 26.5 of Baker et al., “CMOS Circuit Design, Layout and Simulation,” IEEE press 1998, also show circuitry for providing additional current at an output node of a first stage to attempt to control hysteresis. This circuit suffers from the same drawbacks as described above.
In other attempts to introduce controlled small amounts of hysteresis, a reference voltage is shifted based on the output state of the receiver. Although some controllability is achieved, the switching process takes too long to effectively help suppress noise spikes. It also requires two reference voltage generators, which cause additional current consumption. See e.g., U.S. Pat. No. 4,775,807.
In U.S. Pat. No. 4,745,365, the solution described consumes even more power by utilizing two receivers with offset VREF. Both receivers have to run at the same speed.
Therefore, a need exists for an apparatus for reliably controlling hysteresis for noise suppression in analog to digital conversions.
SUMMARY OF THE INVENTION
A receiver circuit, in accordance with the present invention, includes a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier, and a second stage includes an input coupled to the output of the first stage. The second stage also includes a logic gate coupled to the output of the first stage, the logic gate having an output representing the output of the receiver circuit, and a feed back element coupled from the logic gate output and connecting to a switching element. The switching element, being responsive to the logic gate output, switches a current source on and off to adjust a switchpoint of the receiver circuit.
Another receiver circuit, in accordance with the present invention, includes a first stage having an input for receiving input signals. The first stage includes an amplifier with a first node employed as an output and a second node. A second stage has an input coupled to the first node. The second stage further includes a logic gate having an input coupled to the first node, the logic gate having an output representing the output of the receiver circuit, and a switching element coupled to the first node and being responsive to the first node for switching a current source on and off such that the current source adjusts a current at the first node to control a switchpoint at the logic gate output. A feed back element is coupled to the switching element and connects to the second node of the amplifier for providing feedback for adjusting the current at the first node.
In other embodiments, the switching element may include a transistor or a pair of transistors. The pair of transistors may include one P-channel transistor and one N-channel transistor. The current source may be coupled in series with the P-channel transistor and/or in series with the N-channel transistor. The amplifier of the first stage may include a transconductance amplifier or may include a differential amplifier including a base current source having a base current output therefrom and the current source is adjusted in accordance with the base current. The current at the output of the first stage may be adjusted by between about 1% to about 20%. The receiver includes a hysteresis, which may be controlled in accordance with a linear relationship with current from the current source. The receiver circuit may be included on a semiconductor chip. The receiver circuit input signals may include analog signals and the receiver circuit preferably suppresses noise of the analog signals. The logic gate output may include a digital logic state. The receiver circuit may include a power down circuit for turning the amplifier off when inactive. The logic gate may include an inverter.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4431930 (1984-02-01), Monticelli
patent: 4575859 (1986-03-01), Ollendick
patent: 4745365 (1988-05-01), Ugenti
patent: 4775807 (1988-10-01), Bukowski, Jr.
patent: 5065412 (1991-11-01), Schenk
patent: 5327072 (1994-07-01), Savignac et al.
patent: 5640104 (1997-06-01), Matsubara
patent: 5796281 (1998-08-01), Saeki et al.
patent: 5808496 (1998-09-01), Thiel
patent: 6163190 (2000-12-01), Takai et al.
Figures from: Baker et al.,CMOS Circuit Design, Layout and Simulation, IEEE Press, 1998.
Houghton Russ
Kiehl Oliver
Braden Stanton C.
Infineon - Technologies AG
Wells Kenneth B.
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