Receiver with quadrature decimation stage, method of processing

Details Receiver with quadrature decimation stage, method of processing Receiver with quadrature decimation stage, method of processing

1995-09-05

1998-07-21

Vo, Don N.

Pulse or digital communications

Receivers

Angle modulation

375346, 375350, H04L 2714

Patent

active

057844143

ABSTRACT:
In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).

REFERENCES:
patent: 5214678 (1993-05-01), Rault et al.
patent: 5272534 (1993-12-01), Vromans et al.
patent: 5572249 (1996-11-01), Ghosh
Crochiere et al., Multirate Digital Signal Processing, p. 79.

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