Receiver scheme for synchronous digital transmission

Details Receiver scheme for synchronous digital transmission Receiver scheme for synchronous digital transmission

2006-03-01

2009-08-18

Ha, Dac V (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000, C370S503000, C370S516000

Reexamination Certificate

active

07577221

ABSTRACT:
A method, apparatus and system for improving the tolerance for timing jitter noise by eliminating the need to recover clock information from the input signal. There is no need to communicate clock synchronization information between transmit and receive gateways. In addition, the new receiving scheme can work in burst mode in its true sense, i.e., recovering data bits from the first incoming bit after an arbitrary period of time without transmitting.

REFERENCES:
patent: 5121413 (1992-06-01), Voegtly et al.
patent: 5689507 (1997-11-01), Bloks et al.
patent: 6671343 (2003-12-01), Ito
patent: 2004/0264612 (2004-12-01), Allen
patent: 2007/0025484 (2007-02-01), Laine et al.
patent: 0 452 023 (1991-10-01), None
patent: 04 260248 (1992-09-01), None
International Search Report and Written Opinion in corresponding PCT/US2007/004855, Jul. 9, 2007, Lucent Technologies Inc.

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