Receiver input voltage protection circuit

Details Receiver input voltage protection circuit Receiver input voltage protection circuit

1997-03-21

1998-09-29

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, H02H 900

Patent

active

058153543

ABSTRACT:
An off-chip receiver circuit for interfacing an integrated circuit of a 2.5 Volt CMOS technology to a 3.3 Volt LVTTL bus. The off-chip receiver includes protection circuitry for preventing overstressing of the gate oxide caused by undershoot/overshoot peaks of -1 volt to 6 volts on the input.

REFERENCES:
patent: 4405964 (1983-09-01), Woods et al.
patent: 4580063 (1986-04-01), Torelli et al.
patent: 4835650 (1989-05-01), Epstein
patent: 5036215 (1991-07-01), Masleid et al.
patent: 5126596 (1992-06-01), Millman
patent: 5528447 (1996-06-01), McManus et al.

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