Receiver having clock phase memory for receiving short preamble

Details Receiver having clock phase memory for receiving short preamble Receiver having clock phase memory for receiving short preamble

1993-10-19

1995-01-17

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701053, 3701001, 371 54, 375108, 375111, H04J 306

Patent

active

053831888

ABSTRACT:
A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is detected and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value, the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to the decoded signal from being overwritten with a subsequent clock phase signal.

REFERENCES:
patent: 4404680 (1983-09-01), Perkins
patent: 4975929 (1990-12-01), Apple et al.
patent: 5123013 (1992-06-01), Hirayama
patent: 5299187 (1994-03-01), Tabu et al.

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