Receiver having an integrated clock phase detector

Details Receiver having an integrated clock phase detector Receiver having an integrated clock phase detector

2007-02-27

2007-02-27

Burd, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S316000

Reexamination Certificate

active

10192602

ABSTRACT:
Receiver is provided having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling instants of a reception signal which is transmitted from a transmitter (2) with a transmission filter via a transmission channel (3) to the receiver (1). The receiver has at least one matched filter (8) and at least one frequency matched filter (9). The magnitude of a first convolution product of the impulse response of the transmission filter, of the transmission channel (3) and of the matched filter (8), for the maximization of the signal
oise power ratio (SNR) of the reception signal, is maximal at the desired sampling instants. The transfer function FMF (f) of the frequency matched filter (9) is the first derivative in the frequency domain of the transfer function ME (f) of the matched filter (8), in which case at least one multiplier (11) is provided, which multiplies an output signal of the matched filter (8) by an output signal of the frequency matched filter (9) to form a clock phase deviation detection signal (TP).

REFERENCES:
patent: 3771051 (1973-11-01), Abbe
patent: 3993956 (1976-11-01), Gilmore et al.
patent: 5601083 (1997-02-01), Anderson
patent: 5793796 (1998-08-01), Hulbert et al.
patent: 6219374 (2001-04-01), Kim et al.

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