Pulse or digital communications – Receivers
Reexamination Certificate
2007-11-13
2007-11-13
Fan, Chieh M. (Department: 2611)
Pulse or digital communications
Receivers
C375S346000, C375S348000
Reexamination Certificate
active
10015848
ABSTRACT:
A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator (14) for deriving a demodulated bit rate signal, means (36) for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means (28, 38) for selecting the threshold value for comparison with the current bit signal (Sn) in response to a sequence of N bits (where N is at least 2) (Bn-1, Bn-2) received prior to the current bit (Bn) and means (38, 40) for using the current bit to update the selected threshold value.Also disclosed is a method of dc offset correction.
REFERENCES:
patent: 5459762 (1995-10-01), Wang et al.
patent: 5670951 (1997-09-01), Servilio
patent: 5761251 (1998-06-01), Wender
patent: 5825243 (1998-10-01), Sato
patent: 6046643 (2000-04-01), Kranz
patent: 6272193 (2001-08-01), Eglit
patent: 0469647 (1992-02-01), None
patent: 0702475 (1996-03-01), None
patent: 0912020 (1999-04-01), None
Japanese Patent Publication S60-208145 English Translation; Document PTO 05-2678; 1985.
Patent Abstracts of Japan, Sugiyama Fumio, “Data Decision Circuit,” Publication No. 60208145, Oct. 19, 1985, Application No. 59062124, Mar. 31, 1984.
Minnis Brian J.
Moore Paul A.
Payne Adrian W.
Fan Chieh M.
NXP B.V.
Perilla Jason M.
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