Receiver frequency offset bias circuit for TDM radios

Details Receiver frequency offset bias circuit for TDM radios Receiver frequency offset bias circuit for TDM radios

1989-01-05

1991-06-25

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

455231, H04J 312

Patent

active

050273523

ABSTRACT:
An improved bias control circuit (FIG. 2) is disclosed for a radio receiver (122) used in a communication system wherein a signalling preamble is sent prior to sending other information. The bias circuit (140) rapidly determines the DC voltage level representing the average frequency of the received signalling preamble (215), develops a DC bias voltage (275) proportional to the error in frequency between the receiver and the transmitted signal, and then selectively applies this bias voltage to the series coupling capacitor (240) located between the receiver detector (121) and the receiver processing circuitry (123). The circuit is adapted for a 0.2 GMSK receiver in a TDMA communication system, where a known 1100 bit synchronization preamble is sent in each user's TDM time slot.

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