Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-03-02
2002-10-22
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S280000, C370S296000, C370S314000, C370S343000, C370S468000, C370S516000
Reexamination Certificate
active
06470035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiver for receiving a signal transmitted by a time-division multi-access (TDMA) method as used in a cellular telephone network like the Personal Handyphone System (hereinafter “PHS”.
2. Description of the Prior Art
In a receiver (portable terminal) for receiving a signal transmitted by a time-division multi-access method as used in the PHS, the clock signal that is transmitted together with the data signal from a base station so as to be used for the demodulation of the data signal and the clock signal that is generated within the receiver for the processing of the demodulated data signal are asynchronous with respect to each other and have different frequencies. This makes it inevitable that the demodulated data signal is processed by a processing circuit (for example, a TDMA protocol circuit) that operates asynchronously with respect thereto, and thus causes jitters.
For this reason, a conventional receiver is provided with a jitter elimination circuit as shown schematically in FIG.
9
. This jitter elimination circuit employs a FIFO (first-in-first-out) memory
60
. The reproduced data RD
1
and the reproduced clock RCLK that are obtained through demodulation of a received signal by a demodulator are fed to the memory
60
so that the reproduced data RD
1
is stored in the FIFO memory
60
in synchronism with the reproduced clock RCLK. Then, the reproduced data is retrieved as RD
2
from the FIFO memory
60
in synchronism with the clock CLK output from an oscillator provided within the receiver.
Since the frequency of the reproduced clock RCLK, which is a reproduction of the clock transmitted from the base station, is different from that of the clock output from the oscillator, the received data is first stored in the FIFO memory
60
in synchronism with the operation timing of the transmitting side, and is then retrieved therefrom in synchronism with the operation timing of the receiving side. This helps eliminate jitters. The retrieved data RD
2
is then subjected to signal processing, such as waveform shaping and decoding, performed by a TDMA protocol section. In a case where the receiver is a PHS receiver, the processed data is output as sounds from a loudspeaker under the control of a CPU (central processing unit).
In a conventional receiver, the writing/reading operation against the FIFO memory
60
is reset for restarting (i.e. initialized) at the end of a receiving session, and therefore the writing/reading operation lasts for a comparatively long time interval (5 milliseconds) that corresponds to one frame in PHS communication. On the other hand, as described previously, the clock on the transmitting side (i.e. the transmitted clock) and the clock generated by an oscillation circuit on the receiving side have different frequencies. The difference in timing between these two clocks (i.e. the phase difference between the two clocks) becomes larger as time passes. This requires that, in the jitter elimination circuit shown in
FIG. 9
, the writing operation and the reading operation be performed at increasingly distant locations from each other, and accordingly that the FIFO memory
60
have an unduly large storage capacity as achieved by the use of, for example, RAM
1
to RAM
10
. Note that RAM
1
to RAM
10
each correspond to, for example, one bit of data.
Moreover, a large loss of time arises between the time point when the reproduced data RD
1
is stored in the FIFO memory
60
and the time point when it is retrieved as the reproduced data RD
2
, and this causes an undesirable delay in the processes performed by the receiver, for example, for achieving synchronism with the received signal and for searching for the base station that offers the best communication quality.
SUMMARY OF THE INVENTION
An object of the present invention is, in a receiver for receiving a signal transmitted by a time-division multi-access method, to minimize the storage capacity of the memory used by a jitter elimination circuit and minimize the delay from reception of a signal until starting of signal processing.
To achieve the above object, according to one aspect of the present invention, a receiver for receiving a signal transmitted by a time-division multi-access method is provided with: a signal strength detection circuit for detecting whether the signal strength of a signal transmitted by a time-division multi-access method is stronger than a predetermined level; a demodulator for demodulating the signal to output reproduced data and a reproduced clock; an oscillator for outputting an internal clock; a memory to which the reproduced data is written in synchronism with the reproduced clock and from which the reproduced data is read in synchronism with the internal clock; and an initialization circuit for initializing the timing with which the reproduced data is written to and read from the memory.
According to another aspect of the present invention, a receiver for receiving a signal transmitted by a time-division multi-access method that divides one frame into a plurality of communication slots in conducting communication is provided with: a detection circuit for detecting whether a received RF signal is stronger than a predetermined level; a demodulation circuit for demodulating the received RF signal to obtain therefrom reproduced data and a reproduced clock; an oscillation circuit for generating an internal clock; a jitter elimination circuit for eliminating jitters from the reproduced data by writing the reproduced data to a memory in synchronism with the reproduced clock and reading the reproduced data from the memory in synchronism with the internal clock; a processing circuit for decoding the reproduced data after jitter elimination; and an initialization circuit for initializing the jitter elimination circuit in accordance with a result output from the detection circuit.
REFERENCES:
patent: 5210773 (1993-05-01), Schmid et al.
patent: 5754961 (1998-05-01), Serizawa et al.
patent: 5764648 (1998-06-01), Yamane et al.
Arent Fox Kintner Plotkin & Kahn
Ly Anh-Vu H
Rohm & Co., Ltd.
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