Receiver for communication

Details Receiver for communication Receiver for communication

1996-07-11

2004-03-09

Liu, Shuwang (Department: 2634)

Pulse or digital communications

Receivers

C375S346000, C714S715000, C714S758000, C714S765000

Reexamination Certificate

active

06704371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiver including a data processing unit adapted so as to correct two-bit errors in received data by using a cyclic redundancy check (CRC) code.
The present invention relates to a receiver including a data processing unit for determining errors in data to be checked by using the cyclic redundancy check (CRC) code.
The present invention also relates to a receiver including an ID controlling portable synchronous serial data receiving apparatus having a timer function.
The present invention further relates to a receiver including an ID controlling portable serial data receiving apparatus used for a radio paging apparatus (hereinafter referred to as a pager) or the like.
2. Description of the Related Art
As a circuit for correcting errors within received data encoded by a CRC code, a circuit shown in
FIG. 10
is known for example. An error correction circuit
100
shown in
FIG. 10
comprises a shift register circuit
105
for holding data to be checked SIG having a certain number of bits in response to a clock signal CLK
2
, a syndrome generating circuit
103
for generating syndromes by implementing a modulo-two arithmetic on the data to be checked SIG in response to a clock signal CLK
1
and a decoder ROM
300
for decoding syndrome data generated by the syndrome generating circuit
103
.
The decoder ROM
300
is arranged so as to instruct to make a correction on an error bit indicated by the syndrome data. The error in the received data is corrected by turning a selection signal SELECT to a “H” level with a predetermined timing and supplying one pulse as the clock signal CLK
2
to the shift register circuit
105
. The resultant data is held within the shift register circuit
105
by being shifted by one bit.
A data processing circuit for detecting a boundary of words utilizing error detection by means of BCH code is known to be used in a paging decoder for example to synchronize bit serial input data transmitted per bit in a time-division manner with the internal operation. The prior art data processing circuit of this type is arranged so as to detect errors in input data having a predetermined number of bits N by means of the BCH code by N times, to acquire next one bit anew when it is determined that there exists an error and to repeat the same process for detecting errors again by N times until it is determined that there exists no more error.
FIGS. 19 through 24
show one example of the prior art data processing circuit of this type. The data processing circuit
101
shown in
FIGS. 19 through 24
comprises a data register
102
, a syndrome generating circuit
103
and a switching circuit
224
for selectively supplying either input data RD from an input terminal
223
or an output of the data register
102
to an input terminal
223
of the data register
102
in response to a selection control signal SL.
The data register
102
is a shift register circuit having a known structure for holding data supplied to its input terminal by acquiring it on a bit-by-bit basis in response to a clock pulse CL supplied from a clock input terminal
225
every time when the clock pulse CL is input. The held data may be taken out of its output terminal
246
in response to the clock pulse CL.
The syndrome generating circuit
103
is a circuit for generating a syndrome by acquiring the input data RD in response to a the clock pulse CL supplied via an AND gate
252
when the selection control signal turns to “H” level and by implementing modulo-two arithmetic. A logical circuit
106
determines whether a value of the generated syndrome is 0 or not.
The result determined by the logical circuit
106
is supplied as a set signal to a flip-flop
243
which has been put into a reset state by a first set signal RT
1
from a terminal
250
when a check pulse CH is added from a terminal
251
.
The data processing circuit
101
operates as follows. This will be explained with reference to FIG.
25
. At first, when the first reset signal RT
1
and a second reset signal RT
2
supplied to a terminal
226
turn to “L” level for a short time at time T
1
, the data register
102
, the syndrome generating circuit
103
and the flip-flop
243
are reset, respectively, thereby completing their initialization. After that, 31 clock pulses CL are output when the selection control signal SL is at the “L” level and thereby 31 bits of input data RD is taken into the data register
102
.
Next, when the selection control signal SL is switched from a “L” level to “H” level at time T
2
, a loop structure in which an output of the data register
102
is returned to its input is formed and the 31 bits of data held in the data register
102
is cyclically shifted per bit by 31 clock pulses CL supplied after time T
2
.
At the same time, those 31 clock pulses CL are supplied also to the syndrome generating circuit
103
via an AND gate
252
opened by the selection control signal SL and thereby the syndrome for the 31 bits of data held in the data register
102
is calculated.
A value of the syndrome is stored in the flip-flop
243
by the check pulse CH output at time T
3
. If the value of the syndrome at this time is 0, a level of the detection terminal
245
turns to “H”, meaning that the word boundary could have been detected. However, if the value of the syndrome is a number other than 0, data of the next bit is taken in to be checked.
That is, after turning the level of the selection control signal to “L” at time T
4
, only one clock pulse CL is given at time T
5
to input one new bit data to the data register
102
and the syndrome generating circuit
103
is reset by the first reset signal RT
1
at time T
6
.
Then, the level of the selection control signal SL is turned from “L” to “H” at time T
7
to supply 31 clock pulses CL again to execute the calculation of a syndrome for the new set of input data held in the data register
102
.
Thus, the acquisition of one bit of data and the calculation of a syndrome are repeatedly executed until the value of the syndrome becomes 0, i.e. until the word boundary is detected.
As a synchronous serial data receiving apparatus, one as shown in
FIG. 27
in block diagram form has been used in the past. This receiving apparatus has bit synchronizing means and word synchronizing means and determines whether data should be received or not by determining whether it is in a state synchronous or asynchronous to a signal to be transmitted.
FIG. 29
shows a transition of receiving state of the prior art serial data receiving apparatus. This is considered to correspond only to RUN mode in FIG.
28
and only the receiving state shifts between an asynchronous state and a synchronous state in response to detection and non-detection of a synchronous code.
In
FIG. 27
, a timer counter
112
and a timing generating circuit
113
connected to an oscillation circuit
111
supply a timer function and operation timing clocks of each part, respectively. At first, the bit synchronizing means
118
establishes a bit synchronism with an input signal input from a data input terminal
117
. Next, the word synchronizing means
119
establishes a word synchronism. When the word synchronism has been established, the word synchronizing means
119
outputs a control signal to the timing generating means
113
and starts to receive ID and data. The received ID is compared with a content in ID storage means
122
by ID collating means
121
. When the ID is collated without any trouble, a control signal is output from the ID collating means
121
to the timing generating means
113
to continue to receive the data. When the ID cannot be collated, the receiving is terminated. The received data is once stored in data storage means
120
and is output from a data output terminal
124
via an output circuit
123
.
The ID storage means
122
is normally composed of a register. The content therein is written generally from a control input terminal
116
during the initialization. There is a possibility that an erroneous operati

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