Receiver circuits for generating digital clock signals

Details Receiver circuits for generating digital clock signals Receiver circuits for generating digital clock signals

2007-11-13

2007-11-13

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S070000, C327S291000

Reexamination Certificate

active

11275537

ABSTRACT:
A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

REFERENCES:
patent: 5367204 (1994-11-01), Mattison
patent: 6288577 (2001-09-01), Wong
patent: 6320406 (2001-11-01), Morgan et al.
patent: 6650149 (2003-11-01), Wong
patent: 6753701 (2004-06-01), Chang
patent: 6791369 (2004-09-01), Hattori
patent: 6898724 (2005-05-01), Chang
patent: 6989695 (2006-01-01), Dike et al.
patent: 7061296 (2006-06-01), Friedrich et al.

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