Receiver circuit with smart squelch

Details Receiver circuit with smart squelch Receiver circuit with smart squelch

1991-10-15

1994-02-08

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

375104, 375 5, 375 17, 307 58, 307234, 328111, H04B 110

Patent

active

052854817

ABSTRACT:
A receiver circuit relies on four novel pulse width timer/integrators to filter input data signals having a frequency less than a preselected maximum and greater than a preselected minimum. The circuit also rejects a single sine wave cycle. If an input pulse greater than a preselected maximum pulse width is encountered during data reception, then reception activity is terminated. A preferred embodiment of the receiver circuit implements IEEE 802.3 10 Base-T Ethernet receiver requirements utilizing a unique pulse width timer design.

REFERENCES:
patent: 3686438 (1972-08-01), Rousseau
patent: 3821563 (1974-06-01), Warren
patent: 3863244 (1975-01-01), Lichtblau
patent: 4078204 (1978-03-01), Gauthier
patent: 4486752 (1984-12-01), Chihak

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