Receiver circuit and receiver circuit testing method

Details Receiver circuit and receiver circuit testing method Receiver circuit and receiver circuit testing method

2007-03-21

2010-12-28

Payne, David C (Department: 2611)

Telecommunications

Receiver or analog modulated signal frequency converter

Measuring or testing of receiver

C455S067140, C375S316000, C375S354000, C375S373000, C375S375000, C375S376000, C327S147000, C327S156000

Reexamination Certificate

active

07860472

ABSTRACT:
A delay means, in response to a delay control signal, performs delay control of the phase of a clock input signal, and outputs it. A selector means, during a speed test, selects a clock input signal from among a clock input signal from a delay unit, and the input signal from an external terminal. A conversion means samples the signal outputted from the selector means based on the sampling clock signal, converts a signal format and outputs it. A clock data recovery means generates a sampling clock signal having a phase depending on the signal inputted to the conversion means, and supplies it to the conversion means. By monitoring the control code for controlling the phase of the sampling clock, a correlation is obtained between a delay variation amount and a code variation amount, and a speed test is performed.

REFERENCES:
patent: 7092689 (2006-08-01), Boecker et al.
patent: 7251764 (2007-07-01), Bonneau et al.
patent: 7251765 (2007-07-01), Kushiyama et al.
patent: 7349506 (2008-03-01), Shizuki
patent: 2006/0192622 (2006-08-01), Narita
patent: 2003-337159 (2003-11-01), None
patent: 2005-77274 (2005-03-01), None
patent: 2005-257376 (2005-09-01), None

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