Receiver capable of reducing power consumption in a PLL circuit

Details Receiver capable of reducing power consumption in a PLL circuit Receiver capable of reducing power consumption in a PLL circuit

1993-10-18

1995-03-07

Chin, Stephen

Pulse or digital communications

Receivers

Automatic frequency control

375376, 375317, 329307, 455260, 455265, 331 14, H04L 2714

Patent

active

053965213

ABSTRACT:
In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. A duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short. The offset frequency is detected by a frequency detector which produces a control signal appearing only when the offset frequency is present outside of the predetermined range. The control signal is sent to a control circuit for controlling battery saving operations of the VCO and the PLL circuit.

REFERENCES:
patent: 4673892 (1987-06-01), Miyashita et al.
patent: 4916405 (1990-04-01), Keate et al.
patent: 5065107 (1991-11-01), Kumar et al.
patent: 5091921 (1992-02-01), Minami

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