Receiver architecture using mixed analog and digital signal...

Details Receiver architecture using mixed analog and digital signal... Receiver architecture using mixed analog and digital signal...

2006-06-20

2006-06-20

Tran, Khai (Department: 2637)

Pulse or digital communications

Transceivers

C375S232000

Reexamination Certificate

active

07065133

ABSTRACT:
There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.

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