Receiver architecture

Details Receiver architecture Receiver architecture

2006-05-23

2006-05-23

Bayard, Emmanuel (Department: 2634)

Pulse or digital communications

Receivers

C375S356000, C713S401000

Reexamination Certificate

active

07050512

ABSTRACT:
An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control. In one embodiment, the variable delay is set such that the reference signal is made to coincide approximately with the midpoint of a data period of the data stream. With the ability to adjust the variable delay, the receiver is able to derive a proper reference signal regardless of the alignment of the data stream.

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