Receiver and receiving-decoding method

Details Receiver and receiving-decoding method Receiver and receiving-decoding method

1999-10-27

2003-08-05

Kelley, Chris (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C348S725000

Reexamination Certificate

active

06603816

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a receiver and a receiving-decoding method, and more particularly, is suitably applied to a receiver for receiving, for example, digital television broadcasts and outputting an obtained transport stream to an external device and also inputting a transport stream from an external device and decoding it.
2. Description of the Related Art
Digital television broadcasting has already started whereby a video signal is digitalized in accordance with the compressing encoding method such as the moving picture experts group phase 2 (MPEG 2) method and broadcasts it on ground waves or satellite waves.
In such digital television broadcasting, the audience needs a digital-broadcast receiver-decoder referred to as an integrated receiver decoder (IRD) which receives and decodes the ground waves and satellite waves.
In
FIG. 1
,
1
denotes a digital-broadcast receiver-decoder as a whole and an antenna
5
receives broadcast radio waves S
1
and supplies it to a front end
10
. The front end
10
demodulates the broadcast radio waves S
1
, generates a transport stream S
10
composed of successive transport stream (TS) packets, and outputs the stream S
10
to a decipherer
12
. The decipherer
12
deciphers each enciphered TS packet in the case when each TS packet is enciphered and supplies it to a divider
15
.
The divider
15
extracts desired TS packets from the transport stream S
10
, divides them into audio TS packets and video TS packets and supplies them to a decoder
16
. The decoder
16
decodes the audio TS packets S
15
A and the video TS packets S
15
V supplied from the divider
15
in accordance with the MPEG 2 method, and outputs them as an audio signal S
16
A and a video signal S
16
V to an external device.
In this case, the front end
10
generates a byte clock S
11
synchronous with the transport stream S
10
when the transport stream S
10
is generated by demodulating the broadcast waves S
1
and outputs the byte clock S
11
to the decipherer
12
and the divider
15
. The byte clock S
11
is a sync signal for synchronizing and transferring data. The front end
10
, decipherer
12
, and divider
15
operate in accordance with the byte clock S
11
and thereby transfer TS packets composing the transport stream S
10
synchronously with the byte clock S
11
.
In this kind of digital-broadcast receiver-decoder, it is possible to use a high-speed digital data interface such as an institute of electrical and electronics engineers (IEEE) 1394, output and store a transport stream obtained by receiving broadcast radio waves into a digital recorder such as an externally-set digital video tape recorder (VTR) via the digital data interface, and also input and decode the transport stream stored in the digital recorder via the digital data interface.
However, when a transport stream is inputted via the digital data interface, it is possible that the byte clock of a digital-broadcast receiver decoder (that is, the byte clock of a transport stream obtained by receiving broadcast waves) would not coincide with the byte clock of a transport stream inputted via the digital data interface, that is, data transfer rates would not coincide with each other. Moreover, when the byte clock of the transport stream inputted via the digital data interface is faster than that of the digital-broadcast receiver-decoder, a problem occurs that some of the TS packets are not transferred from the digital-broadcast receiver-decoder, which could lead into a decoding trouble.
Furthermore, there can be a case in which digital broadcasts are not received when inputting a transport stream from the digital data interface. In which case, the front end
10
cannot generate a byte clock, which can be an obstacle to the operation of the digital-broadcast receiver-decoder.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of this invention is to provide a receiver and a receiving-decoding method having a simple configuration to receive digital broadcasts, and output the obtained transport stream to an external device, and also to decode a transport stream inputted from the external device.
The foregoing object and other objects of the invention have been achieved by the provision of a receiver which comprises: a receiving part for receiving and demodulating the digital broadcasts to output the first transport stream; a digital interface for receiving the second transport stream supplied from an external device; and a decoding processor for decoding the first transport stream received in the receiving part or the second transport stream received in the digital interface. The decoding processor changes clocks for transferring a transport stream depending on which of the first and second transport streams is being decoded.
Further, the present invention provides a receiving-decoding method for receiving digital broadcasts comprising the steps of: receiving and demodulating the digital broadcasts in the receiving part so as to output a first transport stream; receiving a second transport stream supplied from an external device in a digital interface; transferring to a decoding processor and decoding the first transport stream received in the receiving part or the second transport stream received in the digital interface; and changing clocks used for transferring the transport stream depending on which of the first and second transport streams is being decoded.
Because a clock corresponding to the transfer rate of a transport stream to be decoded is selected, it is possible to decode all data strings without fail.
Moreover, because the third clock used to transfer the second transport stream is generated by frequency-dividing a second clock necessary for the operation of the digital interface, the configuration is simplified without separately using a clock generating circuit.


REFERENCES:
patent: 5920572 (1999-07-01), Washington et al.
patent: 6034732 (2000-03-01), Hirota et al.
patent: 6101195 (2000-08-01), Lyons et al.
patent: 6363061 (2002-03-01), Yuzawa

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