Receiver and digital phase-locked loop for burst mode data recov

Details Receiver and digital phase-locked loop for burst mode data recov Receiver and digital phase-locked loop for burst mode data recov

1989-07-28

1991-08-13

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

341 70, H04L 2722

Patent

active

050401939

ABSTRACT:
A digital data receiver and digital phase-locked loop for providing rapid acquistion and decoding of burst mode data signals, such as Manchester encoded data, without ambiguity. A 180.degree. phase mis-lock detector and phase connector is provided to eliminate any phase-lock ambiguities that may occur. The mis-lock detector utilizes a Manchester data violation detector to determine if the correct phase of sample clock from the digital phase-locked loop is being used for decoding the Manchester data. The digital phase-locked loop utilizes a digital delay line with multiple taps, the appropriate tap, corresponding to a desired phase of a reference clock, is selected as the optimal sample clock. A phase detector determines the difference in phase, measured by the number of taps of the delay line, between the sampling clock phase and the incoming data transitions. The difference is accumulated in an integrator to select the optimal sampling clock phase tap. The phase correction of the sample clock results from switching to a tap on the delay line opposite to the tap being used as the sample clock. Typically, only three data transitions are needed for phase lock.

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"Encoding Schemes in Serial Data Communications", Electronic Engineering, Jul. 1981, pp. 117 through 127.
"A CMOS Ethernet Serial Interface Chip", 1984 IEEE International Solid-State Circuits Conference, pp. 184 and 185.

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