Receiver

Details Receiver Receiver

2005-09-06

2005-09-06

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S295000, C455S069000

Reexamination Certificate

active

06940925

ABSTRACT:
A receiver detects a highly precise approximate value of the power of a reception signal with a high speed. A first comparator outputs a larger of a component I and component Q of a reception signal as a first output value and a smaller as a second output value. A 3-bit shift register multiplies the first output value by ⅛, a subtractor subtracts the by-⅛-multiplied value from the first output value, and a 1-bit shift register multiplies the second output value by ½. A 2-bit shift register multiplies the by-½-multiplied value by ¼, a first adder adds the first output value and the by-¼-multiplied value, and a second adder adds an output value from the subtractor and an output value from the 1-bit shift register. A second comparator outputs the value of a larger result of the two additions as an approximate power of the reception signal.

REFERENCES:
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patent: 6667965 (2003-12-01), Yamaura et al.
patent: 6690922 (2004-02-01), Lindemann
Goodman, David, J. Wireless Personal Communications Systems, Jan. 1998, Addison Wesley Longman Inc., vol. II, pp. 140-149.
Goodman, David, J. Wireless Personal Communications Systems, Jan. 1998, Addison Wesley Longman Inc., vol. II, pp. 140-149.

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