Received data recovering device

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Details

C375S354000, C714S012000

Reexamination Certificate

active

10373077

ABSTRACT:
A received data recovering device that can follow a rapid change in phase of data in data communication, thereby to prevent lowering of the data transmission efficiency, samples a baseband signal in a shift register group of a clock phase detecting circuit using an N-times (N is an integer equal to or greater than 2) frequency relative to the baseband signal, and outputs to a field phase detecting circuit the number of bits required by each of fields per N, the field phase detecting circuit detecting not only a synchronization word, but also error data with respect to fields of a packet header and a Forward Error Correction (FEC) code depending on existence of data and outputting optimum clock phase information to a First In First Out (FIFO).

REFERENCES:
patent: 5535252 (1996-07-01), Kobayashi
patent: 5861925 (1999-01-01), Fujitaka
patent: 6266378 (2001-07-01), Jeon
patent: 6327319 (2001-12-01), Hietala et al.
patent: 6563897 (2003-05-01), Kitta
patent: 6956921 (2005-10-01), Hansson
patent: 2002/0080898 (2002-06-01), Agazzi et al.
patent: 2003/0210755 (2003-11-01), Franca-Neto
patent: 06-252964 (1994-09-01), None
patent: 09-018465 (1997-01-01), None

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