Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
1999-12-21
2001-09-11
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C375S371000
Reexamination Certificate
active
06288656
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to transceiver applications involving transmitting and receiving parallel data. More specifically, the present invention is directed to receiving and regenerating parallel data words which have been broken into smaller data words and serially transmitted over multiple channels.
2. Background
In many transceiver applications, large parallel data words such as sixty-four bit words are broken up on the transmitting chip into smaller parallel data words such as eight bit words. As illustrated in
FIG. 1
, the smaller parallel data words are then serially transmitted over multiple channels at a higher speed. Thus, the number of output pins on the transmit chip and input pins on the receive chip is reduced, for example, from sixty-four to eight. On the receiving chip, the high speed serial data is then appropriately deserialized to regenerate the original sixty-four bit word.
Although smaller parallel data words are being transmitted over multiple channels, on a system level the transceiver should function as a single-channel, sixty-four bit transceiver. To achieve this functionality, receivers in each of the higher speed channels recover clock based on the incoming serial data and generate eight bit parallel data words timed to a channel word clock. The word clock is a division of the recovered clock. The eight bit data words from each of the channels are then transferred from their own channel word clock domain to a single receiver clock domain to form the originally transmitted sixty-four bit data word. However, since the eight bit parallel data words travel on separate channels, the skew between these channels can create problems. The first problem involves aligning the eight bit parallel data words across parallel data channels so they are properly regrouped with other eight bit parallel words, and the second problem involves framing the serial data in each separate channel into eight bit parallel data words.
The first problem encountered in regenerating parallel data words from multiple channels is word alignment across parallel data channels, which is generally illustrated by the timing diagram in FIG.
2
. The timing diagram shows the problem of aligning data on the same clock edge across multiple channels using two channels as an example. A transmitter, breaks up a sixteen bit word into eight bit words A
0
-A
7
and A
8
-A
15
which are serialized and transmitted over channel one and channel two respectively. The receiver is supposed to regenerate the sixteen bit word on its own receiver clock. However, the channel one word clock and the channel two word clock on the two receive channels may not be exactly in phase, and the skew between the two channels may cause the wrong bits from channel two to be re-timed and grouped with the wrong bits from channel one. The timing diagram of
FIG. 2
shows how the misalignment of received data and the out-of-phase channel word clocks between receive channels can cause an incorrect regrouping of the eight bit words from each channel. It is apparent from the diagram that in re-timing the eight bit word outputs from each channel, the re-timing edge of the receiver clock has missed the correct group of channel two data is bits, A
8
-A
15
, and has instead regenerated a sixteen bit word containing correct channel one data but erroneous channel two data.
Prior methods for solving the problem of aligning data words across multiple serial data channels include the use of slave channel architecture as illustrated by the block diagram of FIG.
3
. The block diagram of
FIG. 3
depicts a typical receive deserializer circuit using two serial data channels as an example. Briefly, in a typical single channel receive deserializer circuit as represented by the master channel
300
of
FIG. 3
, a sampling flip flop
302
receives serial data and samples it with the rising edge of the recovered clock. The recovered clock runs at the data rate frequency and is aligned to the serial data transition edge by a clock recovery module
304
so that all the sampling edges are in the middle of the data windows. The recovered clock is the source for eight phase clocks generated by a clock generator
306
. The serial data is sampled by the eight phases to generate eight bits. The eight bits are finally re-timed on one of the phases, channel word clock to form a parallel data word.
In the multi-channel receive deserializer circuit which uses slave channel architecture to align data words across channels, as illustrated in the block diagram of
FIG. 3
, a single channel is chosen as the master channel
300
. The master channel
300
performs clock recovery
304
using a local clock and serial data it receives. The recovered clock from the master channel
300
is then also used by the receivers in all the slave channels
310
to sample serial data input to each channel, thereby properly aligning all the sampled serial data across channels on the same clock edge.
However, the use of slave channel architecture to solve the problem of aligning data words across multiple serial data channels has limitations which often necessitate implementing rigorous and costly design standards when designing and fabricating these circuits. Using slave channel architecture requires that the skew between the serial data inputs across the channels be tightly controlled. The timing diagram of
FIG. 4
illustrates the significant problem encountered when using the slave channel architecture of FIG.
3
. Since the use of slave channel architecture employs just one clock recovery module
304
in a master channel
300
and uses the recovered clock to deserialize data in all the channels, any skew between serial data received in a slave channel
310
and serial data received in the master channel
300
directly reduces the setup/hold margin available at the slave channel
310
sampling flip flop
312
. Rxd
1
of
FIG. 4
represents serial data input to the master channel
300
of FIG.
3
. The clock recovery module
304
generates recovered clock by aligning the negative edge of the local clock with the data transition edge in order to ensure that a sufficient setup/hold margin exists at the master channel
300
sampling flip flop
302
when retiming the data with the positive edge of the recovered clock. However, as shown in the timing diagram of
FIG. 4
, the skew between the rxd
2
serial data from the slave channel
310
, and the rxd
1
serial data from the master channel
300
, reduces the net setup/hold margin at the slave channel
310
sampling flip flop
312
by the amount of skew. If sufficient skew exists between the master channel
300
and any slave channel
310
, the result can be not enough setup/hold margin in the slave channel
310
to permit the sampling flip flop
312
to re-time the rxd
2
serial data to the recovered clock from the master channel
300
.
Once the serial data across the parallel data channels is aligned to the same clock, the second problem of framing the data into the proper parallel words in each channel must also be solved. When framing serial data into an eight bit parallel word in a single channel, a simple receiver deserializer demultiplexes sampled serial data and regenerates the eight bit parallel data words sent by a transmitter. However, the receiver has no information as to which bit of the eight bit parallel word is bit zero, the least significant bit (LSB), or which bit is bit seven, the most significant bit (MSB). Thus, information regarding the boundary of the eight bit parallel word has been lost in its transmission. The result is incorrectly framed parallel data words at the receiver which contain some bits belonging to the previous eight bit word or which contain some bits belonging to the next eight bit word.
Referring again to
FIG. 3
, the block diagram further illustrates a commonly used method for solving the data framing problem which will be discussed with reference to the master channel
300
only, as a single channel example. This prio
LSI Logic Corporation
Nguyen John
Young Brian
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