Receive deserializer circuit for framing parallel data

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S371000, C341S100000

Reexamination Certificate

active

06862296

ABSTRACT:
A receive deserializer circuit which frames parallel data utilizes a skip-bit technique for aligning a predefined data reference pattern with a word clock. The receive deserializer circuit includes a sampling flip flop which receives serial data including a data reference pattern. The sampling flip flop samples and retimes the serial data to a recovered clock. A demultiplexer then deserializes the retimed serial data into a parallel data word which is timed to a word clock from a clock generator. A comparator makes comparisons of the parallel data word with a preset data reference pattern until a match results. A logic controller interprets whether the output of the comparator is a match and generates a shift pulse following each comparison which does not result in a match. The clock generator divides the recovered clock into eight phase clocks. One of the phase clocks is a word clock. Each time the clock generator receives a shift pulse from the logic controller, it disables all the phase clocks by one bit period. This results in a one is bit shift in all the clocks and a one bit shift in the parallel data generated on word clock each time there is no match from the comparator. When a match occurs, no shift pulse is generated by the logic controller, and the predefined data reference pattern and subsequent data words received on word clock are properly framed.

REFERENCES:
patent: 4411007 (1983-10-01), Rodman et al.
patent: 4680779 (1987-07-01), Wakerly
patent: 5398249 (1995-03-01), Chen et al.
patent: 5420895 (1995-05-01), Kim
patent: 6288656 (2001-09-01), Desai

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Receive deserializer circuit for framing parallel data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Receive deserializer circuit for framing parallel data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Receive deserializer circuit for framing parallel data will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3455105

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.