Receive clock deskewing method, apparatus, and system

Details Receive clock deskewing method, apparatus, and system Receive clock deskewing method, apparatus, and system

2005-12-28

2008-10-21

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S232000

Reexamination Certificate

active

07439788

ABSTRACT:
An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

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Hatakaeyama, Atsushi, “A 256-Mb SDRAM Using a Register-Controlled Digital DLL”,IEEE Journal of Solid-State Circuit, vol. 32, No. 11, (Nov. 1977), pp. 1728-1734.

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