Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-08-14
2001-07-31
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S474000, C370S395430
Reexamination Certificate
active
06269096
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to asynchronous transfer mode (ATM) communication and, more particularly, to receive and transmit blocks for asynchronous transfer mode (ATM) cell delineation.
BACKGROUND OF THE INVENTION
Asynchronous transfer mode (ATM) communication systems are widely used for network communications. In general, ATM communication protocols involve stacks having several layers including a physical layer as the lowest layer. The ATM physical layer typically involves the movement of cells between source and target physical layer devices. The cells are often moved across a bus in smaller parallel sets of data. When the data reaches the target device, the cell is reconstructed and then sent up the stack to its final destination. One example of an ATM physical layer protocol is the Utopia 2 protocol. In implementing a physical layer bus, one problem that arises is cell delineation and the transfer of cells across the physical bus.
SUMMARY OF THE INVENTION
In accordance with the present invention, receive and transmit blocks for asynchronous transfer mode (ATM) cell delineation are disclosed that provide advantages over conventional cell delineation schemes.
According to one aspect of the present invention, a receive block for asynchronous transfer mode (ATM) cell delineation has a plurality of cell delineation blocks. Each cell delineation block is coupled to receive an associated serial bit stream, and each cell delineation block operates to identify ATM cell boundaries in the serial bit stream and to convert ATM cell payloads to parallel data words. The receive block also has a memory which has a plurality of memory blocks organized with each memory block associated with a cell delineation block. Each of the memory blocks has a plurality of ATM cell storage locations. A memory controller is coupled to the cell delineation blocks and the memory. The memory controller operates to read data words from the cell delineation blocks and to write data words to one of the cell storage locations in associated memory blocks. A bus controller is coupled to the memory controller and to the memory. The bus controller operates to interface with an ATM physical layer, to receive a memory status signal from the memory controller and to provide signals to the memory for communicating an ATM cell across the ATM physical layer. According to one implementation, the bus controller further receives address mode/select signals and operates to respond to one of a plurality of subsets of port addresses on the ATM physical layer responsive to the address mode/select signals.
According to another aspect of the present invention, a transmit block for asynchronous transfer mode (ATM) cell delineation has a bus controller that operates to interface with an ATM physical layer. The bus controller receives ATM cells across the ATM physical layer and converts ATM cell payloads to output parallel data words. The transmit block further has a plurality of queue memories that each have a plurality of cell storage locations. A plurality of queue select devices are coupled to the bus controller and receive the output parallel data words. Each queue select device provides the output parallel data words to one of the plurality of cell storage locations in an associated queue memory. A plurality of cell delineation blocks each receive parallel data words from an associated queue memory. Each cell delineation block operates to convert parallel data words to a serial bit stream carrying ATM cell payloads. According to one implementation, the bus controller further receives address mode/select signals and operates to respond to one of a plurality of subsets of port addresses on the ATM physical layer responsive to the address mode/select signals.
A technical advantage of the present invention is the use of a memory controller in the receive block which interfaces between cell delineation blocks and memory such that one block of memory can service all receive cell delineation blocks.
Another technical advantage is the use of a bus controller that can respond to different port addresses based upon input settings. This allows the same bus controller design to be used for different ports on the same physical layer bus. Further, the reduction in the number of ports reduces the load seen by the physical layer bus.
Other technical advantages should be readily apparent to one of ordinary skill in view of the description, drawings and claims.
REFERENCES:
patent: 4771425 (1988-09-01), Baran et al.
patent: 4819228 (1989-04-01), Baran et al.
patent: 4903261 (1990-02-01), Baran et al.
patent: 4975906 (1990-12-01), Takiyasu et al.
patent: 4985889 (1991-01-01), Frankish et al.
patent: 5020058 (1991-05-01), Holden et al.
patent: 5059925 (1991-10-01), Weisbloom
patent: 5072449 (1991-12-01), Enns et al.
patent: 5088032 (1992-02-01), Bosack
patent: 5115431 (1992-05-01), Williams et al.
patent: 5119403 (1992-06-01), Krishnan
patent: 5128945 (1992-07-01), Enns et al.
patent: 5224099 (1993-06-01), Corbalis et al.
patent: 5255291 (1993-10-01), Holden et al.
patent: 5274631 (1993-12-01), Bhardwaj
patent: 5274635 (1993-12-01), Rahman et al.
patent: 5274643 (1993-12-01), Fisk
patent: 5313454 (1994-05-01), Bustini et al.
patent: 5317562 (1994-05-01), Nardin et al.
patent: 5359592 (1994-10-01), Corbalis et al.
patent: 5394394 (1995-02-01), Crowther et al.
patent: 5422880 (1995-06-01), Heitkamp et al.
patent: 5430715 (1995-07-01), Corbalis et al.
patent: 5434863 (1995-07-01), Onishi et al.
patent: 5452306 (1995-09-01), Turudic et al.
patent: 5461624 (1995-10-01), Mazzola
patent: 5473599 (1995-12-01), Li et al.
patent: 5473607 (1995-12-01), Hausman et al.
patent: 5509006 (1996-04-01), Wilford et al.
patent: 5517488 (1996-05-01), Miyazaki et al.
patent: 5519704 (1996-05-01), Farinacci et al.
patent: 5555244 (1996-09-01), Gupta et al.
patent: 5561663 (1996-10-01), Klausmeier
patent: 5561669 (1996-10-01), Lenney et al.
patent: 5570360 (1996-10-01), Klausmeier et al.
patent: 5583862 (1996-12-01), Callon
patent: 5598581 (1997-01-01), Daines et al.
patent: 5604741 (1997-02-01), Samueli et al.
patent: 5612957 (1997-03-01), Gregerson et al.
patent: 5617417 (1997-04-01), Sathe et al.
patent: 5617421 (1997-04-01), Chin et al.
patent: 5666353 (1997-09-01), Klausmeier et al.
patent: 5673265 (1997-09-01), Gupta et al.
patent: 5691997 (1997-11-01), Lackey, Jr.
patent: 5729546 (1998-03-01), Gupta et al.
patent: 5732079 (1998-03-01), Castrigno
patent: 5737526 (1998-04-01), Periasamy et al.
patent: 5737635 (1998-04-01), Daines et al.
patent: 5740171 (1998-04-01), Mazzola et al.
patent: 5740176 (1998-04-01), Gupta et al.
patent: 5742604 (1998-04-01), Edsall et al.
patent: 5742649 (1998-04-01), Muntz et al.
patent: 5764636 (1998-06-01), Edsall
patent: 5764641 (1998-06-01), Lin
patent: 5765032 (1998-06-01), Valizadeh
patent: 5787070 (1998-07-01), Gupta et al.
patent: 5787255 (1998-07-01), Parlan et al.
patent: 5793763 (1998-08-01), Mayes et al.
patent: 5793978 (1998-08-01), Fowler
patent: 5796732 (1998-08-01), Mazzola et al.
patent: 5802042 (1998-09-01), Natarajan et al.
patent: 5805595 (1998-09-01), Sharper et al.
patent: 5812618 (1998-09-01), Muntz et al.
patent: 5822383 (1998-10-01), Muntz et al.
patent: 5835036 (1998-11-01), Takefman
patent: 5835481 (1998-11-01), Akyol et al.
patent: 5835494 (1998-11-01), Hughes et al.
patent: 5835725 (1998-11-01), Chiang et al.
patent: 5838915 (1998-11-01), Klausmeier et al.
patent: 5838994 (1998-11-01), Valizadeh
patent: 5859550 (1999-01-01), Brandt
patent: 5864542 (1999-01-01), Gupta et al.
patent: 5867666 (1999-02-01), Harvey
patent: 6026098 (2000-02-01), Kamoi et al.
patent: 6034954 (2000-03-01), Takase et al.
patent: 6041043 (2000-03-01), Denton et al.
patent: 0677941A2 (1995-10-01), None
patent: WO 95/20282 (1995-07-01), None
patent: WO 96/04729 (1996-02-01), None
“Utopia Specification Level 1, Version 2.01,” (af-phy-0017.000),The ATM Forum Committee, Mar. 21, 1994, 19 pages.
Anthony Alles, “ATM Internetworking,”Cisco Systems, Inc., May 1995, 59 pages.
“Utopia Level 2, Version
Botkin Craig D.
Hann William Patrick
Baker & Botts L.L.P.
Chin Wellington
Cisco Technology Inc.
Pham Brenda
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