Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-01-31
2003-12-16
Vu, Huy D. (Department: 2665)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S415000, C370S516000
Reexamination Certificate
active
06665298
ABSTRACT:
FIELD OF THE INVENTION
The present invention in general relates to apparatus and method for reassembling data cells or packets provided by a first communication channel to a stream of data cells or packets to be provided to a second communication channel. The present invention especially relates to an apparatus and a device for reassembling ATM data cells according to a constant bit rate CBR stream of data.
BACKGROUND OF THE INVENTION
Reassembly buffer is adapted to receive data cells from one communication channel and provide data cells to a second communication channel in a manner that compensates for timing differences between the writing of data cells/octets/packets (i.e.-cells) to the reassembly buffer and the reading of data cells out of the reassembly buffer.
Reassembly buffers are used in various applications, such as, but not limited to, circuit emulation systems. One type of circuit emulation circuit is specified in ATM forum specification AF-VTOA-0078. The specification describes a system that allows a plurality of constant bit rate CBR communication channels to be coupled to each other via an Asynchronous Transfer Mode (ATM) network.
ATM has been accepted universally as the transfer mode of choice for Broadband Integrated Services Digital Networks (B-ISDN). The services provided by ATM can be enhanced by providing ATM adaptation layers (AAL). AAL
1
is used to carry certain types of constant bit rate (i.e.- CBR) or “circuit” traffic over ATM networks. ATM is essentially a cell oriented transmission technology and not circuit oriented technology so that the implementation of AAL
1
requires emulation circuit characteristics in order to provide good support for CBR traffic.
ATM forum specification AF-VTOA-0078 specifies circuit emulation services. Two basic systems are disclosed in the specification. First system
19
is shown in FIG.
1
. CBR equipment
20
and
21
are coupled, via CBR service interface
22
and
23
according to ATM Circuit Emulation Services (i.e.- CESs) interworking functions (IWFs)
24
and
25
accordingly. CES IWFs
24
and
25
are coupled, via ATM access interface
26
and
27
to two opposite ends of an ATM network
28
. CES IWFs
24
and
25
extend the CBR equipment
20
and
21
to which they are connected across ATM network
28
in a manner that is transparent to CBR equipment
20
and
21
. The ATM portion of first system
19
should retain its bit integrity. Second system
29
is shown in
FIG. 2
in which ATM CES IWF
30
and
31
are coupled, via ATM access interfaces
32
and
33
accordingly to two opposite ends of an ATM network
34
. Both first and second system
19
and
29
can handle multiple channels. Usually, CBR equipment
20
,
21
,
30
and
31
handle multiple channels by time division multiplexing techniques.
ATM cells are delayed while passing through ATM network
34
. The delay is not constant and can vary within a Cell Delay Variation period (i.e.-CDV). Larger variations in the delay are reflected by longer CDV.
Each of CBS IWFs
24
,
25
,
30
and
31
can be used either to segment a constant bit rate data cell stream or to reassemble a sequence of ATM cells into streams of constant bit rate data cell stream. The reassembly function requires a buffer in which data is stored before it is transferred out of a CES IWF interface. Usually, each channel out of the multiple channels handled by first and second systems
19
and
29
has a dedicated reassembly buffer.
The buffer can overflow and underflow for various reasons: (a) when slight clocking differences exist between a CES IWF in which data cells are segmented and between a CES IWF in which these data cells are reassembled. In such a case there is a difference between a first rate in which data is written in the buffer and a second rate in which data is read out of the buffer. (b) variation in delay over the ATM network, especially when the ATM network is characterized by a relatively large CDV.
When either an overflow and an underflow occur, there is a need to perform a relatively time consuming recovery process. Usually, during an underflow predetermined data cells/packets/octets are provided to the CBR equipment, in order to maintain a constant bit rate. In some devices a last ATM cell that was written in the buffer is retransmitted until the underflow ends. In some devices a predetermined sequence of cells are provided to the CBR equipment until the underflow ends. Usually, during an overflow valid data cells are dropped from the buffer. After the overflow ends there is a need to synchronize to the ATM cell stream.
The buffer contributes to a delay of the CES IWF. Larger reassembly buffers can reduce the occurrence of overruns but can increase the delay of the CES IWF.
There is a need to provide an improved device and method for allowing the reassembly of data with minimal delay and minimizes the occurrence of underflows.
There is a need to provide a device and method for allowing the reassembly of data in a manner that minimizes the occurrence of overflows without needing vary large reassembly buffers.
REFERENCES:
patent: 5297139 (1994-03-01), Okura et al.
patent: 5473604 (1995-12-01), Lorenz et al.
patent: 5539747 (1996-07-01), Ito et al.
patent: 5734653 (1998-03-01), Hiraiwa et al.
patent: 5905870 (1999-05-01), Mangin et al.
patent: 5914954 (1999-06-01), Nakayama
patent: 5978355 (1999-11-01), Yamaguchi
patent: 5982783 (1999-11-01), Frey et al.
patent: 6131144 (2000-10-01), Koppala
patent: 6327249 (2001-12-01), Cookman et al.
Hagai Avi
Katz Itai
Kirzner Eran
Lachman Yuval
Motorola Inc.
Ryman Daniel
Vu Huy D.
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