Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-05-24
2005-05-24
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06898691
ABSTRACT:
This invention discloses a group of instructions, block4and block4v,in a matrix processor16that rearranges data between vector and matrix forms of an A×B matrix of data120where the data matrix includes one or more 4×4 sub-matrices of data160-166.The instructions of this invention simultaneously swaps row or columns between the first140,second142,third144,and fourth146matrix registers according to the instructions that perform predefined matrix tensor operations on the data matrix that includes one of the following group of operations: swapping rows between the different individual matrix registers, or swapping columns between the different individual matrix registers. Additionally, successive iterations or combinations of the block4and or block4vinstructions perform standard tensor matrix operations from the following group of matrix operations: transpose, shuffle, and deal.
REFERENCES:
patent: 5541914 (1996-07-01), Krishnamoorthy et al.
patent: 5875355 (1999-02-01), Sidwell et al.
patent: 6003056 (1999-12-01), Auslander et al.
patent: 6115812 (2000-09-01), Abdallah et al.
patent: 6141673 (2000-10-01), Thayer et al.
patent: 6334176 (2001-12-01), Scales et al.
patent: 6366937 (2002-04-01), Shridhar et al.
patent: 6456838 (2002-09-01), Wang et al.
patent: 6470441 (2002-10-01), Pechanek et al.
patent: 6714690 (2004-03-01), Shimizu
Hartenstein, R.; Coarse Grain Reconfigurable Architectures; Asia and South Pacific Design Automation Conference 2001; 1-30 through Feb. 2, 2001; Yokohama, Japan.
Taveniku, M.; Ahlander, A.; Jonsson, M.; and Svensson, B.; The VEGA Moderatly Parallel MIMD, Moderately Parallel SIMD, Architecture for High Performance Array Signal Processing; International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing; 3-30 through Apr. 3, 1998, Orlando, Florida.
Miyamori, T. and Olukotun, K.; REMARC: Reconfigurable Multimedia Array Coprocessor, IEICE Transactions on Information and Systems E82-D, p. 389 through 397, 2-99.
Lu, G.; Lee, M.; Bagherzadeh, N.; Kuradhi, F.; and Filho, E.; The MorphoSys Parallel Reconfigurable System; in proceedings of Euro-Par 99, Toulouse, France, 9-99.
Blomgren James S.
Harle Christophe
Olson Timothy A.
Booth Matthew J.
Coleman Eric
Intrinsity, Inc.
Matthew J. Booth & Associates PLLC
LandOfFree
Rearranging data between vector and matrix forms in a SIMD... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Rearranging data between vector and matrix forms in a SIMD..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Rearranging data between vector and matrix forms in a SIMD... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3390445