Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-08-16
2004-09-07
Zarneke, David A. (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C174S050510, C174S261000, C257S686000, C257S723000, C257S784000, C361S733000
Reexamination Certificate
active
06787915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacture thereof. In particular, it relates to the construction and a method of manufacturing a multi-chip package (MCP) of the type produced by chip and the construction and a method of manufacturing a wafer-level CSP (chip size package).
2. Description of Related Art
FIG. 1
shows an example of a conventional semiconductor device of an MCP (multi-chip package) construction of the type obtained by laminating chips.
FIG. 1A
is a plane view seen from above of the arrangement relationships of the structural elements of a semiconductor device. This shows the construction of the underside of the sealing portion.
FIG. 1B
is a cross-sectional view of a prior art semiconductor device.
As shown in FIG.
1
A and
FIG. 1B
, a first semiconductor element (first element)
504
provided with a plurality of bonding pads
503
is stuck onto the upper surface of a substrate
500
using first adhesive
502
. A second semiconductor element (second element)
508
provided with a plurality of bonding pads
507
is stuck onto the upper surface of first element
504
using second adhesive
506
. A plurality of bonding posts
510
are provided in the region of the upper surface of substrate
500
other than the region where the first element
504
is mounted. These bonding posts
510
and the bonding pads
503
on first element
504
are connected by first wires
512
constituted by fine metallic leads. Bonding pads
507
on second element
508
and other bonding posts
510
on the upper surface of substrate
500
are connected by second wires
514
constituted by fine metallic leads. As shown in
FIG. 1B
, sealing portion
516
is formed by sealing such that the entirety of first elements
504
, second elements
508
, first wires
512
and second wires
514
on the upper surface of substrate
500
is covered by molded resin.
In the conventional wafer-level CSP construction, for example, a further plurality of layers are laminated on the semiconductor element formed with a plurality of bonding pads on the surface. The bonding pads of the semiconductor element and the desired wiring patterns formed on the upper surface of the uppermost layer of the aforementioned plurality of layers are electrically connected by means of through-holes and metallic wiring formed in this plurality of layers. These laminated structures are sealed by molded resin. In a well known construction, the conductive posts are formed so as to be electrically connected with the desired wiring patterns of, for example, the uppermost layer, and the surface of the conductive posts is exposed on the mounting surface of the molded resin.
In the manufacture of such a wafer-level CSP, in a wafer formed with a plurality of semiconductor elements, the step of lamination onto the semiconductor element, the wiring step and the sealing step are performed by processing the plurality of elements simultaneously. CSPs are then obtained by dicing the wafer on which the sealing step has been completed, so as to obtain individual semiconductor element units.
However, in a conventional semiconductor device as shown in
FIG. 1
, when connecting second wires
514
to the bonding pads
507
on second element
508
and bonding posts
510
on substrate
500
, depending on the positions of bonding posts
510
, there is a risk of short-circuiting of the first wires
512
and second wires
514
that are used to connect bonding pads
503
of first element
504
and bonding posts
510
on the substrate
500
.
In order to prevent such short-circuiting of the first wires
512
and the second wires
514
, the positions of bonding pads
503
on the first element
504
whereby first wires
512
are arranged and the positions of bonding pads
507
on second element
508
whereby second wires
514
are arranged must be respectively selected such that short-circuiting does not occur. The positions of bonding pads
503
and
507
for which wiring is possible are therefore severely restricted, so the degrees of design freedom of the semiconductor element are reduced.
In order to solve the problems described above, there has been a demand for a construction of a semiconductor device (MCP or wafer-level CSP) which will increase the degree of design freedom of semiconductor elements compared to the prior art and a method of manufacturing such a device easily and at low cost.
Particularly, in a conventional wafer-level CSP, a plurality of layers are laminated on the semiconductor element and the bonding pads are rearranged on the uppermost surface of the layers, so it is not easy to effect further rearrangement in response to demands from the user. Furthermore, in manufacture, it was necessary to redevelop all of the wiring steps and lamination steps onto the semiconductor element: such redevelopment took time.
There has been a demand for a wafer-level CSP construction which makes it easier to reposition the bonding pads compared to the prior art. Further, there also has been a demand for a method of manufacturing such a wafer-level CSP.
Accordingly, one object of the present invention is to provide a semiconductor device, specifically, MCP or wafer-level CSP, having a high degree of design freedom semiconductor elements.
Another object of the present invention is to provide a method of manufacturing such a device easily and at low cost.
Another object of the present invention is to provide a rearrangement sheet applied to a semiconductor device.
Still another object of the present invention is to provide a method of manufacturing such a rearrangement sheet.
SUMMARY OF THE INVENTION
The inventors of the present invention succeeded in developing a novel rearrangement sheet applied to a semiconductor device whereby rearrangement of the bonding pads can easily be performed.
The rearrangement sheet comprises an insulating sheet and conductive metallic patterns formed on this insulating sheet.
The rearrangement sheet is formed as follows.
Specifically, a plurality of masks corresponding to the shape of conductive metallic patterns in single units is provided on an insulating film. Using the masks, a plurality of conductive metal plated patterns in single chip units are formed on the insulating film.
After removing the masks, the insulating film is divided into each single chip unit to obtain a plurality of rearrangement sheets.
For example, in an MCP of the type in which chips are laminated, the rearrangement sheet may be interposed between the first element and second element of a structure in which the first element and second element are laminated in this order on a substrate. When bonding posts formed on the substrate, the bonding pads of the first element and the bonding pads of the second element must be respectively connected, the bonding posts and the conductive metallic patterns of the rearrangement sheet are connected and these conductive metallic patterns and the bonding pads of second element are connected. Next, the bonding posts and the bonding pads of the first element are subjected to wire bonding as normally. Since the conductive metallic patterns can be provided in desired positions on the rearrangement sheet, connection between the bonding pads of the second element and the bonding posts can be effected irrespective of the positions of the metal wires that connect the bonding pads of the first element and the bonding posts. So, by the rearrangement sheet of the present invention, for example in the example described above, rearrangement of the bonding pads of the second element can easily be performed, thereby making it possible to increase the degrees of design freedom of the second element.
As an example of use of a rearrangement sheet according to the present invention, for example the case of application to a wafer-level CSP may be considered. In a wafer-level CSP, the rearrangement sheet is provided in a region of the semiconductor element provided with the plurality of bonding pads where the bonding pads are not formed.
Saeki Yoshihiro
Uchida Yasufumi
Oki Electric Industry Co. Ltd.
Rabin & Berdo PC
Sarkar Asok Kumar
Zarneke David A.
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