Realtime systolic, multiple-instruction, single-data parallel co

Details Realtime systolic, multiple-instruction, single-data parallel co Realtime systolic, multiple-instruction, single-data parallel co

1988-11-23

1992-08-04

Shaw, Gareth D.

Boots, shoes, and leggings

395200, 395 10, 3642747, 3642768, 3642818, 3642712, 364228, 3642281, 3642282, 3642292, 364DIG1, G06F 1580

Patent

active

051367173

ABSTRACT:
A computer system especially for solution of real time inference problems is disclosed. The system includes a systolic cellular processor which provides predictable and responsive real time operation and fine grain programmability. The system comprises a plurality of separate processor cells each having its own local memory, the cells running simultaneously and operative to execute their respective program instructions. A global memory is coupled via a global bus to the processor cells and provides data to the cells and stores data from the cells. The bus provides effectively simultaneous access of all cells to the global memory. A further feature of the system is a novel parallel programming language using English syntax and which provides synchronous and predictable binding of code to each cell. A graphic work station is provided as a user interface to provide visual access to each cell or to cell groups for ease of control. The system can also function to emulate large scale integrated circuit processors by reason of the fine grain programmed operation of the system.

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