Realtime clock with page mode addressing

Details Realtime clock with page mode addressing Realtime clock with page mode addressing

1994-11-22

1997-02-25

Lane, Jack A.

395412, 39542104, 39542107, 3954211, 395402, G06F 1200, G06F 1202, G06F 934, G06F 926

Patent

active

056066805

ABSTRACT:
A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

REFERENCES:
patent: 4317169 (1982-02-01), Panepinto, Jr. et al.
patent: 5220201 (1993-06-01), Kawasaki et al.
patent: 5469548 (1995-11-01), Callison et al.

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