Real time rank ordering logic circuit

Communications: electrical – Digital comparator systems

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36471501, G06F 702

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active

049581414

ABSTRACT:
A ranking circuit operable in real time to rank a set of periodically changing sample values, having a series of sequentially clocked storage registers for sequentially storing the sample values, a series of corresponding first comparators for comparing each sample stored to the incoming sample, a summer for summing the outputs of the first comparators to assign an initial rank to the incoming sample, a series of rank registers for storing the initial rank value and a rank value corresponding to each sample in the sample registers, increment/decrement logic for adjusting each rank in the respective rank registers as each new sample is received, logic for effectively excluding a target sample from the ranking process, and logic for outputting a sample value of selected rank during each clock cycle. Optional logic for automatically adjusting the selected rank based on the relative amplitudes of the samples being ranked is also disclosed.

REFERENCES:
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patent: 3848586 (1974-11-01), Suzuki et al.
patent: 3927391 (1975-12-01), Cantrell
patent: 4119946 (1978-10-01), Taylor
patent: 4255740 (1981-03-01), Ferrie
patent: 4628483 (1986-12-01), Nelson
patent: 4649394 (1987-03-01), Minker et al.
1985 International Symposium on Circuits & Systems, 5-7 June 1985, Kyoto (JP), vol. 3 IEEE; N. Kanpopoulos et al.; "On the Architecture of a Monolithic Median Filter with Variable Window Widths", pp. 1537-1538.
Systems & Computers in Japan, vol. 17, No. 1, Jan. 1986, Scripta Technica, Inc. (New York, US), T. Nakayama et al.; "An Algorithm to Perform the Rank Filter and its Application", pp. 19-25.

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