Real time quiescent current test limit methodology

Details Real time quiescent current test limit methodology Real time quiescent current test limit methodology

1997-09-05

2000-01-11

Dutton, Brian

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438 17, H01L 2100

Patent

active

060135336

ABSTRACT:
A method of sorting dies found on wafers is disclosed. Each wafer is part of a set of wafers and the sorting rejects some of the dies. The method first selects an acceptable deviation within an abstract distribution. A respective test parameter is measured and recorded for each die in the set of wafers, and a distribution of the test parameter across the set of wafers is calculated. Based on this distribution and the acceptable deviation, a test parameter limit is set and any dies having a test parameter value greater than the limit are rejected.

REFERENCES:
patent: 4243937 (1981-01-01), Multani et al.
patent: 5286656 (1994-02-01), Keown et al.
patent: 5841293 (1998-11-01), Leas

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