Real time programmable digital register analyser

Details Real time programmable digital register analyser Real time programmable digital register analyser

1976-06-18

1977-08-02

Dildine, Jr., R. Stephen

Registers

Transfer mechanism

Traveling pawl

235153AC, 235153AK, H03K 518, G08B 2900

Patent

active

040398145

ABSTRACT:
An apparatus is provided for analyzing output signals of digital devices. The apparatus comprises a plurality of comparison registers which evaluate the digital output signals, each comparison register including rotary switches for decoding the output signals under analysis. Programming switches permit to generate a function signal through at least one output channel provided in each comparison register when the output signals and the decoded value of said register are in a predetermined relationship. The operations of all comparison registers are selectively controlled by means of a logic circuit. As a result, a function signal is issued by the comparison register through a given channel in accordance with a predetermined program set by the switches and under the control of the logic circuit means, whenever a predetermined relationship exists between the output signals from the digital device under analysis and the value decoded on the comparison register.

REFERENCES:
patent: 3892955 (1975-07-01), Maejima
patent: 3988603 (1976-10-01), Griffin

Affiliated with

Also associated with

Rating

Real time programmable digital register analyser does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Real time programmable digital register analyser, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Real time programmable digital register analyser will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2300865