Real time parser for data packets in a communications network

Multiplex communications – Wide area network – Packet switching

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370392, G06F 1300

Patent

active

058058087

ABSTRACT:
A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

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