Real time observation serial scan test architecture

Details Real time observation serial scan test architecture Real time observation serial scan test architecture

1994-06-27

2000-03-07

Assouad, Patrick

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

714727, H03K 300

Patent

active

060352620

ABSTRACT:
Logic circuitry in the form of an integrated circuit includes a number of scannable registers located at various locations of the logic circuitry to continuously sample signal states thereat. In response to signalling from a maintenance diagnostic processor the scannable registers can be commanded to freeze their content for extraction and observation to determining the operating condition of the logic circuitry.

REFERENCES:
patent: 4827476 (1989-05-01), Garcia
patent: 4945536 (1990-07-01), Hancu
patent: 5210759 (1993-05-01), De Witt et al.
patent: 5253255 (1993-10-01), Carbine
patent: 5293123 (1994-03-01), Jordan et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5384533 (1995-01-01), Tokuda et al.
patent: 5392296 (1995-02-01), Suzuki

Affiliated with

Also associated with

Rating

Real time observation serial scan test architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Real time observation serial scan test architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Real time observation serial scan test architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-372157