Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
2002-04-17
2003-05-27
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Multiplexing
C365S189020
Reexamination Certificate
active
06570809
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a flash memory device with quick data duplication.
2. Description of the Prior Art
Portable electronic products are widely popular among consumers. Portable electronic products including digital cameras, cellular phones, video game systems, and personal digital assistants use flash memory devices to store data. As a result, flash memory technology is constantly improving because of the demands of consumers for portable electronic products.
Flash memory uses a non-volatile memory structure, and controls a threshold voltage of a memory cell to store binary data such as a “0” or a “1”. A key design feature of flash memory is that the data stored is not lost when the power supply is shut down.
The complex nature of programming and erasing flash memory devices leads to a major challenge. Specifically, the write access of flash memory is not as fast as the read access. The time-consuming write access decreases the overall efficiency of the flash memory device. In addition, conventional flash memory devices typically do not allow a processor to issue a read operation command while a program or an erase operation is executed. In most implementations, the processor is required to periodically monitor the status register of the flash memory device to detect the end of a program or an erase operation before initiating a read operation command.
Prior art systems may employ multiple flash memory devices in an attempt to prevent the above defect. In such systems, the processor usually issues a read operation command to one of the flash memory devices while other flash memory devices are undergoing program or erase operations. However, such systems typically suffer from high costs because multiple flash memory devices are implemented even though the capacity of a single flash memory device may adequately accommodate the needs of the particular electronic device.
Please refer to
FIG. 1
, which is a block diagram of a prior art flash memory device
10
. The flash memory device
10
has a plurality of memory sections
12
,
14
(only two memory sections are shown for clarity), and a controller
16
. The memory sections
12
,
14
are respectively associated with status registers
18
,
20
, sense amplifiers
22
,
24
, charge pump circuits
26
,
28
, X-decoders
30
,
32
, and Y-decoders
34
,
36
. The memory sections
12
,
14
each have a plurality of memory cells arranged in a matrix format for storing binary data. The controller
16
controls the operation of the flash memory device
10
via communication with a processor of an application system. The status registers
18
,
20
store the current status (programming, reading, or erasing) of each memory section
12
,
14
. The sense amplifiers
22
,
24
are used for amplifying signals read from the memory cells of the memory sections
12
,
14
to determine the binary data stored in the corresponding memory cells. The charge pump circuits
26
,
28
are used to provide the voltage levels needed for reading, programming or erasing the memory sections
12
,
14
. The X-decoders
30
,
32
and the Y-decoders
34
,
36
enable a selection of a specific memory cell within the memory sections
12
,
14
of the flash memory device
10
.
Multiple X-decoders and Y-decoders permit simultaneous access to more than one memory section
12
,
14
. For example, while the memory section
12
is being erased, the memory section
14
may be simultaneously read. When the memory sections
12
,
14
are required to store the same inputted data, the controller
16
will output the data once to each of the memory sections
12
,
14
. For example, the controller
16
outputs a first address data and the associated input data to the X-decoder
30
, Y-decoder
34
, and charge pump circuit
26
at time T
0
. Then, the controller
16
outputs a second address data and the same input data to the X-decoder
32
, Y-decoder
36
, and charge pump circuit
28
at time T
0
+dT. The flash memory device
10
has only one port for receiving data transmitted from an application system and one buffer for storing the input data temporarily. The delay time dT is required because the identical input data is transmitted to individual memory sections
12
,
14
from the same buffer. Similarly, when the data stored in the memory section
12
is required to be copied to the memory section
14
, the data must first be retrieved from the memory section
12
, and then be outputted to a buffer. The data stored in the buffer will then be written into the memory section
14
after a new writing procedure is executed.
The performance of the flash memory device
10
is affected by repeatedly executing identical operations to achieve the purpose of data duplication. This duplication of data causes overall performance to be poor because of the lengthy data transmission between the memory sections.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a flash memory device with quick data duplication to solve the above-mentioned problem.
Briefly, the claimed invention provides a flash memory device having a control logic for controlling programming, erasing, and reading operations of the flash memory device, a data input buffer for storing input data, a first data bus for transferring the input data received from the data input buffer, and a plurality of memory sections. Each memory section has a plurality of memory cells arranged in a matrix format for storing binary data, a page buffer for temporarily storing data which will be written into a corresponding memory cell, and a data multiplexer connected to the page buffer, the first data bus and a second data bus. The data multiplexer is used for selecting a transmitting path between the page buffer and the first data bus or between the page buffer and the second data bus. When the input data stored in a memory section is to be duplicated into another memory section, each of data multiplexers corresponding to the two memory sections will select a transmitting path between a corresponding page buffer and the second data bus to allow the input data to be duplicated through the second data bus.
It is an advantage of the claimed invention that the flash memory device can directly duplicate data between page buffers. Both the transmitting paths and the time required for transmitting data from one memory section to other memory sections are shortened.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 6279069 (2001-08-01), Robinson et al.
patent: 6282145 (2001-08-01), Tran et al.
patent: 6288724 (2001-09-01), Kumar et al.
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp. 170-171.
e-Memory Technology, Inc.
Hsu Winston
Tran M.
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