Communications: directive radio wave systems and devices (e.g. – Testing or calibrating of radar system – By simulation
Reexamination Certificate
2001-12-27
2002-12-24
Tarcza, Thomas H. (Department: 3662)
Communications: directive radio wave systems and devices (e.g.,
Testing or calibrating of radar system
By simulation
Reexamination Certificate
active
06498583
ABSTRACT:
SCENARIO OF THE INVENTION
1. Field of the Invention
The invention relates in general to a real time target generator, and more particularly, to a real time multiple simulated targets generator.
2. Description of the Related Art
For a missile projection control system, scenarios of the war games are difficult to design and costly. To effectively test the capability of electronic interference suppression, clutter elimination, signal
oise (S/N) ratio gain, and target extracted algorithm of the radar signal processor (SP) of a projection control system; and the effectiveness of a dynamic real time schedule of radar control computer (RCC) responsible for data processing and the search and tracking algorithm, radar multiple simulated targets and scenario generators are required to generate the simulated received waveform, so as to reduce the requirement of the war games.
The conventional simulator employing an independent strap-on system requires synchronous signal and interface to match the system to be measured. Such a simulator has to be made by custom design, and is thus very costly. Moreover, part of the specifications of the system to be measured, such as the waveform modulation method and maximum compression gain, relates the confidentiality of system specification. By using the analog technique, the conventional simulator has a large volume and a blind distance limitation region generated by the simulated target.
SUMMARY OF THE INVENTION
The invention provides a real time multiple simulated targets generator for mono pulse radar. The real time multiple simulated targets generator for mono pulse radar has variable modulation waveform to simulate any radar feedback signal and the versatile scenario in a reduced hardware cost.
The invention provides a real time multiple simulated targets generator for mono pulse radar, which can be applied to a simulation control system of a radar system. The real time multiple simulated targets generator for mono pulse radar comprises at least one signal processor, in which a real time multiple simulated targets generator is built. The real time multiple simulated targets generator comprises a precision timing generator, N (N is an integer greater than or equal to 1) pseudo random noise (PRN) code generators, N digital modulation waveform generators (DMWG), and N extent target generators. Each of the pseudo random noise code generators is coupled to the precision timing generator to receive a timing signal generated thereby, so as to generate a pseudo random noise code. Each of the digital modulation waveform generators is coupled to the precision timing generator to receive the timing signal and coupled to the corresponding pseudo random noise code generator to receive the pseudo random noise code thereof, so as to generate a modulation waveform signal. Each of the extent target generators is coupled to the corresponding digital modulation waveform generator to receive the modulation waveform signal thereof, so as to generate a simulation target signal.
The above precision timing generator further comprises an input register, a time word RAM, an event code RAM, a control FIFO, an address counter, a loop down counter, a reference counter, a comparator, and an output register. The input register receives a data from an external device or circuit. The time word RAM is coupled to the input register to store a plurality of time words. The event code RAM is coupled to the input register to provide at least one start address and a loop count value. The address counter is coupled to the time word RAM, the event code RAM and the control FIFO to address a time word and an event code corresponding to the start address. The loop down counter is coupled to the control FIFO to count down the loop count value. The reference counter is used to provide a time reference count value. The comparator is coupled to the time word RAM and the reference counter to compare the reference count value with the time word values output by the time word RAM, and outputs a time complete signal when the reference count value equals to the time word value. The output register is coupled to the event code RAM and the comparator to output the event code output from the event code RAM while receiving the time complete signal.
The above pseudo random noise code generator further comprises a first register, a second register, a bandwidth selector, a shift register, a counter, a stop signal generator, a multiplexer, an AND gate and a NOR gate. The first register receives a phase seed word (PC) parameter, and the second register receives a phase feedback word (PF) parameter. The bandwidth selector is used to receive a plurality of bandwidth clocks and select a corresponding bandwidth clock signal to output. The shift register is coupled to the first register and the bandwidth selector to receive the PC parameter and the bandwidth clock signal, so as to generate a psendo random sequence. The counter outputs a trigger signal according to a code length. The stop signal generator is coupled to the counter to generate a stop signal according to the trigger signal. The multiplexer is coupled to the shift register to sequentially output each bit of the pseudo random noise code sequence, and is further coupled to the stop signal generator. The output is stopped when the multiplexer receives the stop signal. The AND gate is used to receive the pseudo random noise code sequence and the PF parameter output from the shift register and the second register, respectively. The NOR gate is coupled to an output of the AND gate to feedback the output thereof to the shift register.
The above digital modulation waveform generator further comprises a parameter FIFO, a linear frequency generator, a phase generator, a 2's-complementor, a COS/SIN value generator, a multiplixer, a pre-pulse generator, a complex multiplier, and an select/output apparatus. The parameter FIFO receives a data signal. The linear frequency generator is coupled to an output of the parameter FIFO to generate a linear frequency. The phase generator is coupled to the parameter FIFO and the linear frequency generator to generate a phase according to the pseudo random noise code. The COS/SIN value generator is coupled to an output of the phase generator. The multiplexer receives the data signal, an output of the 2's-complementor, and an output of the COS/SIN value generator. The pre-pulse generator is used to synchronize the analog module. The complex multiplier receives an output of the multiplexer. The select/output apparatus receives outputs of the pre-pulse generator, the complex multiplier and the COS/SIN value generator, and select one of them to output.
The extent target generator further comprises a plurality of programmable digital delayers, a plurality of AND gates and a summation apparatus. The programmable digital delayers are serially connected to each other. The output of each programmable digital delayer is connect to an input of the next programmable digital delay, while the input of the first programmable digital delayer is coupled to the output signal of the digital modulation waveform generator. The AND gate receives the output signal of each programmable digital delay. The summation apparatus is coupled to the output of each AND gate and the output signal of the digital modulation waveform generator to obtain a summation thereof, so as to generate the simulation target signal.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Chen Ming-Chan
Chou Chao-Cheng
Tsai Ming-Fa
Andrea Brian
Chung-Shan Institute of Science and Technology
J.C. Patents
Tarcza Thomas H.
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