Real-time implementation of field programmable gate arrays...

Details Real-time implementation of field programmable gate arrays... Real-time implementation of field programmable gate arrays...

2008-04-29

2008-04-29

Mehta, Bhavesh M. (Department: 2624)

Image analysis

Applications

Motion or velocity measuring

C716S030000, C359S337100, C356S303000

Reexamination Certificate

active

10875102

ABSTRACT:
A Field Programmable Gate Arrays (FPGA) design uses a Coordinate Rotation DIgital Computer (CORDIC) algorithm that can convert a Givens rotation of a vector to a set of shift-add operations. The CORDIC algorithm can be easily implemented in hardware architecture, therefore in FPGA. Since the computation of the inverse of the data correlation matrix involves a series of Givens rotations, the utility of the CORDIC algorithm allows a causal Constrained Energy Minimization (CEM) to perform real-time processing in FPGA. An FPGA implementation of the causal CEM is described and its detailed architecture is also described.

REFERENCES:
patent: 6693970 (2004-02-01), Vankka
patent: 7031992 (2006-04-01), Khan et al.
patent: 2006/0282489 (2006-12-01), Khan et al.
patent: 2006/0285531 (2006-12-01), Howard et al.
Andraka (Andraka, Ray; “A survey of Cordic algorithms for FPGA based computers;” Andraka Consulting Group, Inc.; From Google; 1998).
Ma et al. (Ma, Jun; Parhi, Keshab; Deprettere, Ed; “High-Speed Cordic Based Parallel Weight Extraction For QRD-RLS Adaptive Filtering,” Dept. of Electrical and Computer Engineering, University of Minnesota, Minneapolis and Dept. of Electrical Engineering, Delft University of Technology, 2628 CD Delft, The Netherlands; IEEE; 1998).

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