Real-time implementation of a 8Kbps CELP coder on a DSP pair

Details Real-time implementation of a 8Kbps CELP coder on a DSP pair Real-time implementation of a 8Kbps CELP coder on a DSP pair

1993-03-26

1996-02-13

MacDonald, Allen R.

395 228, G10L 302, G10L 900

Patent

active

054917719

ABSTRACT:
A codec uses low cost digital signal processors (DSPs) to implement the codebook excited linear prediction (CELP) algorithm. The flexible architecture provides a platform for implementing a family of CELP codecs. In a specific example, an 8 Kbps CELP codec is partitioned into parallel tasks for real time implementation on dual DSPs with flexible intertask communication, prioritization and synchronization with asynchronous transmit and receive frame timings. The two DSPs are used in a master-slave pair. Each DSP has its own local memory. The DSPs communicate to each other through interrupts. Messages are passed through a dual port RAM. Each dual port RAM has separate sections for command-response and for data.

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