Real time fault tolerant error correction mechanism

Details Real time fault tolerant error correction mechanism Real time fault tolerant error correction mechanism

1981-09-28

1984-06-19

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

044556551

ABSTRACT:
The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as a data transfer circuit between a disc memory and a processing unit. It operates in two modes: as an encoding system and error detector on a disc write, and as a decoding system and error corrector on a disc read. In its first mode, each block of data from the processing unit is encoded with an error syndrome as it is transmitted to the disc memory. Two identical linear feedback shift registers (LFSR's) are used for error detection purposes. In its second mode, the same two LFSR's are implemented with a buffer memory to achieve real-time error correction. Data flow to the LFSR's from the disc memory is alternated block-by-block, one block being received by one LFSR and the succeeding block being received by the other LFSR. At the same time that data is channeled to a particular LFSR, it is channeled synchronously to the buffer memory. While one LFSR is decoding the incoming block, the other LFSR is providing output signals to correct the previous data block which is leaving the buffer memory as new incoming data arrives.

REFERENCES:
patent: 3825893 (1974-07-01), Bossen et al.
patent: 4058851 (1977-11-01), Scheuneman
patent: 4236247 (1980-11-01), Sundberg
patent: 4249253 (1981-02-01), Gentili et al.
patent: 4276646 (1981-06-01), Haggard et al.

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