Real time debugger for a microcomputer

Details Real time debugger for a microcomputer Real time debugger for a microcomputer

1995-09-11

2001-02-06

Chaki, Kakali (Department: 2762)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C703S028000, C714S037000

Reexamination Certificate

active

06185731

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a microcomputer which has a function of confirming operation of a program or verifying validity of a program.
2. Description of the Prior Art
FIG. 1
is a diagrammatic view showing a conventional system for confirming operation of a program or verifying validity of a program on a microcomputer. Referring to
FIG. 1
, reference numeral
101
denotes a system to be debugged including a microcomputer
102
having a CPU
103
, and
104
a microcomputer provided for debugging a program of the microcomputer
102
and including a dual port RAM
105
and a serial input/output circuit
106
connected to the dual port RAM
105
. Reference numeral
108
denotes an address bus of the microcomputer
102
,
109
a data bus of the microcomputer, and
110
a system bus signal line of the microcomputer. The microcomputer
104
accommodates the address bus
108
, the data bus
109
and the system bus signal line
110
. Reference numeral
107
denotes a serial output data line from the serial input/output circuit
106
. It is to be noted that the system bus signal line
110
transmits system bus signals such as a memory read signal or a memory write signal.
Operation will be described subsequently. It is convenient if the process during or a result of calculation by a program can be monitored in order to confirm operation of the program or verify validity of the program on the microcomputer
102
. The system shown in
FIG. 1
is constructed so as to satisfy such demand. It is to be noted that debugging herein signifies monitoring of data in the RAM during execution of a program. Where the microcomputer
102
of the debug object system
101
is a one-chip microcomputer which includes a ROM, a RAM and so forth built therein, the built-in RAM is used in actual application. However, upon debugging, the dual port RAM
105
on the microcomputer
104
is used as a RAM. In particular, upon debugging, data are written into the dual port RAM
105
and data are read out from the dual port RAM
105
while the microcomputer
102
is executing a program.
In the microcomputer
104
, contents of the dual port RAM
105
are outputted suitably to the outside by way of the serial input/output circuit
106
and the serial output data line
107
. A monitor system placed outside (not shown) having a display unit and an outputting apparatus receives the contents of the dual port RAM
105
from the microcomputer
104
. Data of the RAM of the microcomputer
102
during execution of a program are provided to the monitor system in such a manner as described above. Then, a debugging person determines whether the data obtained at the monitor system are desired data or valid data. Then, based on the determination, the debugging person determines whether or not the program on the microcomputer
102
is valid.
Since the conventional microcomputer
102
is constructed in such a manner as described above, the microcomputer
102
accesses the inside RAM when it is actually working, but it accesses the dual port RAM
105
by way of the address bus
108
, the data bus
109
and the system bus signal line
110
, that is, the external buses when it is debugged. Since the accessing by way of the external bus requires a longer time than the accessing by way of the internal bus, as the bus cycle is raised to a high speed, access to the dual port RAM
105
becomes impossible. In other words, as the bus cycle is raised to a high speed, debugging becomes impossible, and consequently, there is a problem in that there is a limitation in increasing of the speed of the bus cycle. It is to be noted that a microcomputer which has an operation mode for analysis or debugging of software is disclosed in Japanese Patent Laid-Open No. Hei 5-334114.
SUMMARY OF THE INVENTION
The present invention has been made to eliminate such a program as described above, and it is an object of the present invention to provide a microcomputer which enables to monitor data in a RAM on the outside without using an external bus and besides without occupying an internal bus of a CPU.
According to the present invention, a microcomputer comprises a real time debugger which reads out data in the internal RAM when a CPU does not access the RAM and outputs the read out data to the outside if a read address of an internal RAM is received from the outside. The real time debugger confirms whether or not the CPU is accessing the RAM, and reads out data at an address designated from the outside from the RAM when the CPU is not accessing the RAM.
With the microcomputer, data in the RAM can be monitored on the outside without using an external bus, and even if the speed of the operation clocks of the CPU is raised, debugging is still possible.
According to an aspect of the real time debugger, it includes a plurality of address registers for storing address data designating addresses of the RAM supplied from the outside, and an address pointer for designating one of the address registers which corresponds to address data provided for the RAM. In the real time debugger of the construction just described, address data inputted from the outside are successively stored into the address registers, and the address data in the individual address registers are supplied to the RAM side successively in accordance with contents of the address pointer by which one of the address registers is designated.
With the microcomputer of the construction just described, data of a plurality of addresses can be used in a lump, and a monitor system on the outside can use read data efficiently.
The microcomputer may further comprise a local address bus provided between the real time debugger and the RAM, a local data bus provided between the RAM and the real time debugger, a switch for connecting the plurality of address registers of the real time debugger to the local address bus, and a switch for disconnecting an address bus of the CPU from the RAM. The real time debugger of the microcomputer of the construction just described, accesses the RAM by using the local address bus and the local data bus. When the real time debugger accesses the RAM, the switches disconnect the RAM and the CPU from each other.
The real time debugger can read out data of the RAM without occupying the buses of the CPU and does not obstruct operation of the CPU upon debugging.
According to another aspect of the real time debugger of the microcomputer, it further includes a control section for receiving a command including command data designating an operation condition of the real time debugger and address data designating a read address and performing an operation in accordance with the received command. The control section receives a command including command data and address data from the outside and performs such processing as reading out of data from the RAM in accordance with the command data in the received command.
With the microcomputer of the construction just described, a debugging system which can realize various debugging functions by developing an arbitrary command on the monitor system side provided on the outside can be constructed.
According to a further aspect of the real time debugger, it outputs a signal representing that data outputted to the outside is significant. The real time debugger of the construction just described outputs, when it reads out data of the RAM and outputs the data to the outside, to the outside also a signal representing that the data are significant.
With the microcomputer of the construction just described, a period of significant data can be detected readily on the monitor system side provided on the outside, and consequently, the construction of the monitor system can be simplified.
According to a still further aspect of the real time debugger of the microcomputer, it accommodates a reset signal line for transmitting a reset signal from the outside to the real time debugger, and another reset signal line for transmitting a reset signal from the CPU to the real time debugger. The real time debugger of the co

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