Real time binary arithmetic encoding

Coded data generation or conversion – Digital code to digital code converters

Reexamination Certificate

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C341S051000

Reexamination Certificate

active

07026961

ABSTRACT:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.

REFERENCES:
patent: 6646578 (2003-11-01), Au
patent: 6798977 (2004-09-01), Maeda
patent: 6906647 (2005-06-01), Bossen

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