Real-time background legality verification of pin placement

Details Real-time background legality verification of pin placement Real-time background legality verification of pin placement

2011-08-02

2011-08-02

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S116000, C716S118000, C716S122000, C716S132000

Reexamination Certificate

active

07992119

ABSTRACT:
Pin placement legality is verified in real-time in a background to reduce a number of input/output assignment analysis runs during a physical design of a programmable logic device. Edited pin properties are checked quickly in the background against certain rules, and results displayed to a user usually before a new pin is edited. Available and legal positions are found and displayed for a selected pin to reduce errors.

REFERENCES:
patent: 5694604 (1997-12-01), Reiffin
patent: 5805860 (1998-09-01), Parham
patent: 7627838 (2009-12-01), Keswick
patent: 2004/0128626 (2004-07-01), Wingren et al.
patent: 2007/0250800 (2007-10-01), Keswick

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