Readout circuit for a monolithically integrated circuit for line

Details Readout circuit for a monolithically integrated circuit for line Readout circuit for a monolithically integrated circuit for line

1980-07-24

1982-10-05

Edlow, Martin H.

357 24, H01L 2714

Patent

active

043530842

ABSTRACT:
A monolithically integrated circuit for linear image scanning is coupled through clock pulse-supplied transfer gates to a number of readout charge transfer devices and has an overflow drain zone and an overflow gate disposed between the drain zone and the sensors connected to a clock pulse for selectively permitting transfer of charge between the sensors and the drain zone, with the sensors divided into groups representing image lines. The linear image scanning circuit operated by the interlacing method by which partial images are generated by different groups of sensors. The clock pulse controlling the overflow gate restricts the integration times of the various groups of sensors so that during the scanning of the partial images generated thereby, overlapping of the image data of one line of adjacent partial images is eliminated.

REFERENCES:
patent: 4242599 (1980-12-01), Suzuki
patent: 4242694 (1980-12-01), Koike et al.
D. T. Wright, "Solid State Sensors:The Use of a Single Dimension 512 Element Array for Film Scanning", BBC Report RD1973/32, (PH-113), Nov., 1973, pp. 1-17.
J. M. White and S. G. Chamberlain, "A Multiple-Gate CCD-Photodiode Sensor Element for Imaging Arrays", IEEE Transactions on Electron Devices, vol. ED-25, No. 2, Feb., (1978), pp. 125-131.

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